An Improved VLSI Algorithm for Modular Operation in Cryptography

Objectives: This paper presents a new proposed algorithm which performs an efficient modular multiplication method which is advantage because of its reduction in hardware and software. This proposed method implies a systematic approach which increases the parallelism level when compared to the previous versions. Methods/Analysis: Two conventional methods are effectively used to find the modular multiplication output. The previous work effectively combines the first conventional and next two algorithms which are invented to overcome the disadvantages of the first two algorithms. The proposed method effectively eliminates one conventional method. Findings: This process reduces the number of iterations hence, reducing the time consumption required to synthesis the entire algorithm. Thus, the above mentioned method efficiently condenses the hardware utilization for implementing the conventional and previous algorithm so far practiced before. Application/Improvements: This paper replaces the classical algorithm by other method which effectively reduces the number of iterations. This reduction in computation makes a drastic reduction in hardware and time delay to execute the algorithms. This paper shows a modification in the existing parallelism method which further shows a great improvement in reduction of hardware and time delay.