Modified Architecture for Distributed Arithmetic with Optimized Delay using Parallel Processing

In VLSI design of system configuration, the important parameter speed is playing a vital role in the design which is purely determined by the delay of the design. In the delay of the design is arrived by design delay and routing i.e. path delay. Nowadays in the design, the path or routing delay dominates more due to miniaturization of the design. During earlier days design delay dominates more. Because of scaling in the design, it is essential to concentrate more towards routing delay of the design to get the optimized delay in turn optimized speed in trade of with area. In the proposed work, by reviewing different architecture was constructed with different basic module in order to achieve optimized delay which is realized using verilog HDL.