A B C D E F G H I J K L M N O P Q R S T U V W X Y Z All
Hazarathaiah, A.
- A Novel Medical Image Compression Using New Traditional Orthogonal Wavelets
Authors
1 SV College of Engineering, Tirupati, Andra Pradesh-51750, IN
2 JNT University, Kakinada, Andra Pradesh-533003, IN
Source
Digital Image Processing, Vol 5, No 11 (2013), Pagination: 500-507Abstract
Wavelets, from its early age to the present date, are at use in many practical applications. Though it is a single word, it is different in every appearance. In Haar version it appears as though it is so soft and smooth, in Daubechies version db2 and db3 it appear to be a sharp knife, in Coiflet version as a nerve beat. The new wavelets are always needed because one needs a unique tool to a specific problem. In this paper four orthogonal, asymmetric wavelets are proposed and are used in Image compression. The Peak Signal to Noise Ratio (PSNR), Compression Ratio (CR), Decoding, Encoding and transforming times are calculated. The proposed wavelet simulation results show that they are superior to so called traditional wavelets on medical image compression.Keywords
Traditional Wavelets, Basis Function, Filters, Compression.
- FPGA Implementation of High Speed RC4 Algorithm
Authors
Source
Digital Image Processing, Vol 8, No 7 (2016), Pagination: 244-248Abstract
Rivest Code4 Algorithm is most popular Stream Cipher, which is widely used in many security protocols and standards due to its speed and flexibility. A few hardware implementations were previously recommended in the literature with the objective of enhancing the performance, area, or both. In this paper, a new hardware implementation of the RC4 algorithm using FPGA is proposed. The primary thought of this design is the utilization of a dual-port block RAM for image encryption in the FPGA in order to better utilize the available logic and memory resources. Joined with a new pipelined hardware implementation, the new outline accomplishes better performance. The design is portrayed utilizing Verilog HDL and synthesized and implemented using Xilinx 14.1 ISE suite for content encryption as well as Quartus-II 9.1 for image encryption of various FPGA devices. Synthesis results demonstrate that the proposed design accomplishes higher efficiency than previous implementations by diminishing area while keeping up a good throughput.