Design of Two Stage CMOS Comparator with Improved Accuracy in Terms of Different Parameters

The well developing industry of electronics is insistent to low power and high speed and less area ADCs (analog to digital converters). Comparator is device that is especially employed in ADCs, used for division method, associated for square measure and chiefly liable for delay created and power consumption by an ADC. A low power and high speed comparator is needed to satisfy the longer term demands. The circuit conferred during this paper is designed using 0.35μm CMOS technology with 1.65V bias voltage and 12μA bias current. Cadence virtuoso tool is employed for the designing and simulation for the comparator circuit. The correct analysis of propagation delay, settling time, speed of the comparator is mentioned very well in detail.