N. Bala Dastagiri ¹, K. Hari Kishore ¹

Affiliations
1 K. L. University, Green Fields, Vaddeswaram, Vijayawada - 522502, Andhra Pradesh, IN

Abstract

Background/Objectives: The latched regenerative comparator is an essential block in all ADC architectures. It majorly suffers from the non-idealities such as kickback noise, thermal noise and offset voltage. Especially in an ADC implemented in Cardiac IMDs, the generated kickback noise in latched comparator can make a difference to the accuracy, resolution and settling time to an extent. The main objective of this work is to implement a technique for kickback noise reduction in latched comparators. Methods/Statistical Analysis: This work reviews the various architectures of latched comparators implemented in Cardiac IMDs and also make assessment of the available solutions to reduce the generated kickback noise in a latched comparator. The available kickback noise reduction techniques are implemented in SR latched dynamic comparators and resultant findings are compared. Findings: This brief proposes a new solution to cancel out the unwanted charge injections in the comparator and thus reduces the kickback noise effectively. The proposed solution is implemented in the latched comparator with SR latch and also compared with the already available solutions with regard to kickback noise and power dissipation. Application/Improvements: The proposed Kickback noise reduction technique reduces the noise to 40% more when compared with the other techniques and this technique is applicable to the dynamic Comparators used in Cardiac IMDs.

Keywords

Carddiac IMDs, Cmos Technology, Kickback Noise, Latched Comparator, Offset Voltage, Random Noise.

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N. Bala Dastagiri ¹, K. Hari Kishore ¹

Affiliations
1 Department of ECE, KL University, Vijayawada 522502, Andra Pradesh, IN

Abstract

Objectives: The main objective of this work is to explore and investigate the significance of power dissipation and kickback noise in the design of dynamic comparators used in cardiac pacemakers. Methods/Statistics: In this paper a power and noise efficient dynamic comparators are designed for cardiac pacemakers based on conventional dynamic comparators. Results/Findings: It is shown that the dual rail dynamic comparator suffers from low kickback noise but has more power dissipation and vice versa in case of balanced dynamic comparator. From the results it can be noted that either power or kickback noise can be minimized at a time. Application: Pacemakers are cardiac implantable medical devices used to boost up the heart rate. For such devices low power consumption is very vital. Dynamic comparators are power hungry and decision making devices in pacemakers.

Keywords

Comparator, Kickback Noise, Low Power Consumption, Pacemaker.

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M. Hanumanthu ¹, N. Bala Dastagiri ¹, B. Abdul Rahim ², P. Somasundar ²

Affiliations
1 Department of Electronics and Communication Engineering, Annamacharya Institute of Technology and Sciences, Rajampet - 516126, Andhra Pradesh, IN
2 Department of Electronics and Communication Engineering, Annamacharya Institute of Technology and Sciences, Rajampet - 516126, Andhra Pradesh

Abstract

Background/Objective: To design the AND, OR type circuits based on foot based and foot-less based gate domino logic and compare the results. Methods/Statistics: Nowadays VLSI circuits are expected to operate with low power, high speed, less area and noise tolerance. The major challenge in VLSI circuits is to obtain high performance. There are several digital logic techniques available viz. pseudo static CMOS, pass-transistor logic, complementary pass-transistor logic, GDI, dynamic CMOS logic, domino CMOS logic, which can be used to achieve high performance circuits. Findings: Static CMOS circuits have both pull down and pull up networks, but the disadvantage is, total number of transistors in the circuit is more. The dynamic logic circuits overcome the disadvantage of static complementary MOS. On the other side dynamic logic suffers from charge leakage, charge sharing and noise sensitivity, due to sub-threshold leakage current flow in the Pull Down Network (PDN), called stacking effect. When we scale down the technology, these effects will also get increased.

Keywords

Footed, Foot-Less Domino, Power Dissipation

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