Bhagwan Das ¹, M.F.L. Abdullah ¹, Nor Shahihda Mohd Shah ¹, B. S. Chowdhry ², Dil Muhammad Akbar Hussain ³

Affiliations
1 Faculty of Electrical and Electronic Engineering, Universiti Tun Hussein Onn, MY
2 Faculty of Electrical, Electronic and Computer Engineering, Mehran University of Engineering, Technology, Jamshoro, PK
3 Aalborg Aalborg University, DK

Abstract

Information and Communication Technology (ICT) is growing rapidly, and ICT devices are consuming plenty of energy, for communication systems. In Gb/s transmission system high range and high- speed optical transmitter requires high power for transmitting information at long distance. The existing techniques are consuming vast amount of power, exhibits heating effect, and leakage power problems for optical transmitter of 40 Gb/s or more. In this work, an energy efficient 100Gb/s optical DPSK transmitter is designed using UltraScale Field Programming Gate Array (FPGA). The design is realized by controlling the impedance of 100Gb/s optical DPSK transmitter using Digitally Controlled Impedance (DCI) IO (Input/ Output) Standards available on UltraScale FPGA. It is determined that 80% power is reduced using designed 100Gb/s optical DPSK transmitter, for 100 GHz, 300 GHz, 900 GHz and 12 THz using High Speed Low Voltage DCI (HSLVDCI_15) IO Standard compared to optical transmitter design without IO Standard. Furthermore, using designed system 90% leakage power is also reduced. The designed energy efficient optical transmitter can be interfaced with other optical components, to provide the green optical communication.

Keywords

Differential Phase Shift Keying (DPSK), Energy Efficient, Field Programming Gate Array, Laser Signal, Non-Return-to-Zero Modulation, Optical Transmitter.

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Anirudh Khanna ¹, Bhagwan Das ², Bishwajeet Pandey ³, DMA Hussain ⁴, Vishal Jain ⁵

Affiliations
1 Chitkara University, Kalu Jhanda - 174103, Himachal Pradesh, IN
2 University Tun Hussein Onn Malaysia, MY
3 Gyancity Research Lab, IN
4 Aalborg University Denmark, DK
5 Bharati Vidyapeeth’s Institute of Computer Applications and Management (BVICAM), New Delhi – 110063, IN

Abstract

Objectives: With the advent of AI and IoT, the idea of incorporating smart things/appliances in our day to day life is converting into a reality. The paper discusses the possibilities and potential of designing IoT systems which can be controlled via natural language, with help of Quick Script as a development platform. Methods/Statistical Analysis: Quick Script (or QS) is an open-source, easy to learn tool made by our team of student developers for programming virtual conversational entities. This paper focuses on a discussion about how some improvements can be made in the underlying implementation of QS and the resulting uncomplicated and simple platform which can be used to create natural language based IoT systems. It explores the architecture/design pattern required for creating such systems. Findings: This exploration reveals how the idea of turning a simple NLP tool to handling IoT systems can be implemented, and where all the necessary changes/ additions are to be made. The benefits of this will include sharing the power of controlling and even programming (up to some extent) to the user end. As well as providing a simple intermediary to make communication between man and his machines a little more natural. Application/Improvements: It has always been a fantasy in movies to have appliances and gadgets work according to our speech inputs in real time. We humans have always tried to take complete advantage of technologies for living better and working more productively. The idea behind this paper drives for the same cause. Applications of any natural language based service can be endless–ranging from home to industry. With the speech based interaction, this will even help the physically disabled people.

Keywords

Artificial Intelligence, Internet of Things, Natural Language Processing, Quick Script, Smart Devices.

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Bhagwan Das ¹, M.F.L. Abdullah ¹, Mohd. Shah Nor Shahida ¹, Qadir Bakhsh ¹

Affiliations
1 Universiti Tun Hussein Onn Malaysia (UTHM)

Abstract

In optical communication systems, semiconductor lasers are widely in use as an optical source but the performance of laser are limited due to temperature variation, design incompetency, and power consumption issues. The direct output of semiconductor laser may destroy the additional component attached in the system. In this research, semiconductor laser, driver is implemented by utilizing the current mode logic technique to control the output of semiconductor laser. Current Mode Logic (CML) is one of the compatible technique to work integeratedly with optical components. CML based design of semiconductor laser driver has achieved the current ranges from 5.6 mA to 6.8 mA and efficiently working up to 10 GHz frequency and consume 75% less power than typically available laser drivers. In future, the semiconductor laser may have implemented using System on Chip (SoC) configuration to make the design more energy efficient, in terms of temperature sensitivity and power consumption.

Keywords

Current Mode Logic, Driver Circuits, N-Metal Oxide Semiconductor Transistor, Semiconductor Lasers, Switching Efficiency

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Bishwajeet Pandey ¹, Md. Atiqur Rahman ¹, Dil M. Akbar Hussain ², Abhay Saxena ³, Bhagwan Das ⁴

Affiliations
1 Gyancity Research Lab, IN
2 Aalborg University, DK
3 Dev Sanskriti Vishwavidyalaya, Haridwar, IN
4 UTHM, MY

Abstract

The 8-bit design is able to process 256 times input combination in compare to 4-bit vedic multiplier, using approximates 6 times basic elements, 2 times IO buffers, approximate 1.5 times total power dissipation. HSTL_I_12, SSTL18_I and LVCMOS12 are the most energy efficient IO standards in HSTL, SSTL and LVCMOS family respectively. Device static power and design static power are two types of static power dissipation. Device static power is also known as Leakage power when the device is on but not configured. Design static power is power dissipation when bit file of design is downloaded on FPGA but there is no switching activity. Design static power dissipation of 8-bit Vedic multiplier is almost double of design static power dissipation of 4-bit Vedic multiplier. Device static (leakage) power dissipation of 8-bit Vedic multiplier is almost equal to device static power dissipation of 4-bit Vedic multiplier on 40nm FPGA.

Keywords

HSTL, IO Standards, LVCMOS, SSTL, Static Power Reduction, Vedic Multiplier, Voltage Scaling.

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