Indian Journal of Science and Technology

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Digital number system in a computer performs the basic arithmetic operation using multiplier. The functionality of this multiplier can be obtained through addition, subtraction and right shift operations but the utilization of adders, subtractors and shift registers components to perform multiplication is huge. So we proposed the multiplication algorithm for computer by altering the existing booth methodology, which reduces the component and complexity of the multiplication process. The novel algorithm is implemented on pipeline quadratic equations and verified through the simulation result. The arithmetic circuit is written in VHDL and synthesized with Xilinx using Spartan 3 FPGA kit.

Keywords

Computer Arithmetic Multiplication Algorithm, FPGA, Quadratic Equation, VLSI
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