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FPGA Implementation of RA-CORDIC Processor
In processing the real world data Digital Signal Processing algorithms provide unbeatable performance. One of the DSP algorithms is COordinate Rotation DIgital Computer (CORDIC). For real-time airborne computation, CORDIC act as a special purpose digital computer. Basically the CORDIC is categorized in two different styles such as sequential (folded) and combinational (unfolded). This paper presents a novel architecture of CORDIC using redundant arithmetic i.e., RA-CORDIC. The RA-CORDIC structure shows better latency and obtains maximum throughput. The structure has been coded in VERILOG, synthesis analysis are performed using Xilinx ISim tool and targeted on Xilinx FPGA synthesis tool.
Keywords
FPGA, CORDIC Algorithm, Folded & Unfolded Architectures, Redundant Arithmetic
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