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FIR Filter Implementation Using Modified Distributed Arithmetic Architecture


Affiliations
1 Department of Electronics and Communication Engineering, Saveetha Engineering College, Tamil Nadu, 602105, India
 

In this project use Distributed Arithmetic (DA) technique for FIR filter. In this technique consist of Look Up Table (LUT), shift register and accumulator. Based on this technique multipliers in FIR filter are removed. Multiplication is performed through shift and addition operations. The LUT can be subdivided into a number of LUT to reduce the size of the LUT for higher order filter. Each LUT operates on a different set of filter taps. Analysis on the performance of various filter orders with different address length are done using Xilinx synthesis tool. The proposed architecture provides less latency and less area compared with existing structure of FIR filter.

Keywords

FIR, Distributed Arithmetic, LUT
User

  • Kyung-Saeng K, Lee K (2003). Low-power and area efficient FIR filter implementation suitable for multiple tape, Very Large Scale Integration (VLSI) Systems, vol 11, No 1.
  • Meyer-Base U (2004). Digital Signal Processing with Field Programmable Gate Arrays, 2nd Edn., Chapter 2, 60-66.
  • Meyer-Base U (2004). Digital Signal Processing with Field Programmable Gate Arrays, 2nd Edn., Chapter 3, 112-113.
  • Meher P K (2006). Hardware efficient systolization of DA-based calculation of finite digital convolution of finite digital convolution, IEEE Transactions on Circuit and Systems II: Express Briefs, vol 53(8), 707-711.
  • Meher P K, Chandrasekaran S et al. (2008). FPGA realization of FIR filters by efficient and flexible systolization using distributed arithmetic, IEEE Transactions on Signal Processing, vol 56(7), 3009-3017.

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  • FIR Filter Implementation Using Modified Distributed Arithmetic Architecture

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Authors

M. Yazhini
Department of Electronics and Communication Engineering, Saveetha Engineering College, Tamil Nadu, 602105, India
R. Ramesh
Department of Electronics and Communication Engineering, Saveetha Engineering College, Tamil Nadu, 602105, India

Abstract


In this project use Distributed Arithmetic (DA) technique for FIR filter. In this technique consist of Look Up Table (LUT), shift register and accumulator. Based on this technique multipliers in FIR filter are removed. Multiplication is performed through shift and addition operations. The LUT can be subdivided into a number of LUT to reduce the size of the LUT for higher order filter. Each LUT operates on a different set of filter taps. Analysis on the performance of various filter orders with different address length are done using Xilinx synthesis tool. The proposed architecture provides less latency and less area compared with existing structure of FIR filter.

Keywords


FIR, Distributed Arithmetic, LUT

References





DOI: https://doi.org/10.17485/ijst%2F2013%2Fv6i5%2F33250