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Reduction of power dissipation in sequential circuits


Affiliations
1 G.M.R. Institute of Technology, Rajam-532127, Andhra Pradesh, India
2 Aurora Engineering College, Bhongir-508116 Andhra Pradesh, India
 

In this paper, an attempt is made to reduce the power consumption of a synchronous digital system by minimizing the total power consumed by the clock signals. This paper presents a state assignment technique called priority encoding which uses multi-code assignment plus clock gating to reduce power dissipation in sequential circuits. The basic idea is to assign multiple codes to states so as to enable more effective clock gating in the sequential circuit. Experimental results demonstrate that the priority encoding technique can result in sizable power saving.

Keywords

Priority Encoding, Multi Code State Assignment, Clock Gating
User

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  • Reduction of power dissipation in sequential circuits

Abstract Views: 561  |  PDF Views: 83

Authors

B. I. Neelgar
G.M.R. Institute of Technology, Rajam-532127, Andhra Pradesh, India
Prabhu. G. Benakop
Aurora Engineering College, Bhongir-508116 Andhra Pradesh, India

Abstract


In this paper, an attempt is made to reduce the power consumption of a synchronous digital system by minimizing the total power consumed by the clock signals. This paper presents a state assignment technique called priority encoding which uses multi-code assignment plus clock gating to reduce power dissipation in sequential circuits. The basic idea is to assign multiple codes to states so as to enable more effective clock gating in the sequential circuit. Experimental results demonstrate that the priority encoding technique can result in sizable power saving.

Keywords


Priority Encoding, Multi Code State Assignment, Clock Gating

References





DOI: https://doi.org/10.17485/ijst%2F2008%2Fv1i3%2F29222