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Development and Implementation of Parallel to Serial Data Transmitter using Aurora Protocol for High Speed Serial Data Transmission on Virtex-7 FPGA


Affiliations
1 SRM University, Kattankulathur, Chennai - 603203, Tamil Nadu, India
 

The objective of this paper is Development and Implementation of parallel to serial data converter using Aurora protocol for high speed serial data transmission at the rate of 3.125Gbps by using architectural features of Virtex-7 FPGA. It involves the study and configuring the Xilinx Core Generator Tool to achieve the required high speed serial data transmission by using of Aurora 8b/10b Protocol & Multi-Gigabit Transceivers present in Virtex-7 FPGA. Firstly, a 192-bit parallel data is generated using simulators, which is implemented using VHDL language. The 192-bit data is sent to Asynchronous First-In First-Out (AFIFO) as input and produces an output of 32-bit parallel data. This data is sent to the aurora module in parallel form as successive frames (i.e. 6 frames, each frame consists of 4 bytes). Finally, the 192-bit parallel data is transmitted to the receiver module serially over fiber optic cable at the rate of 3.125Gbps using architectural features of virtex7 FPGA. Finally, the data is transmitted on dual independent aurora channels and the entire logic will be tested for its complete functionality in standalone mode by porting on to the Virtex-7 FPGA based custom Hardware.
User

  • Reddy TVB. A real time implementation of high speed data transmission using aurora protocol on multi-gigabit transceivers in Virtex-5 FPGA. International Journal of Research in Computer and Communication Technology. 2012 Aug; 1(3):106–11.

  • Clive MAX Maxfield. The design warriors’ guide to FPGAs; 2004.

  • Athavale A, Christensen C. High speed serial I/O made simple- A designers’ guide with FPGA applications; 2005.

  • Xilinx, Aurora 8b/10b protocol specification, available at “http://www.xilinx.com/support/documentation/ip_documentation/ aurora_8b10b_protocol_spec_sp002.pdf ”, SP002 (v2.2) April 19, 2010.

  • Xilinx, LogiCORE ip aurora 8b/10 v6.2 user guide [Internet]. 2010 Jul 23. Available from: available at http://www.xilinx.com/support/documentation/ip_documentation/ aurora_8b10b_ug353.pdf.

  • Kishore V. Design and implementation of high speed data transmission over dual independent aurora channels on one GTX dual tile usingVirtex-5. 2013 International Journal of Scientific & Engineering Research; 2013.


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  • Development and Implementation of Parallel to Serial Data Transmitter using Aurora Protocol for High Speed Serial Data Transmission on Virtex-7 FPGA

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Authors

C. Mani Pradhitha
SRM University, Kattankulathur, Chennai - 603203, Tamil Nadu, India
S. Kolangiammal
SRM University, Kattankulathur, Chennai - 603203, Tamil Nadu, India

Abstract


The objective of this paper is Development and Implementation of parallel to serial data converter using Aurora protocol for high speed serial data transmission at the rate of 3.125Gbps by using architectural features of Virtex-7 FPGA. It involves the study and configuring the Xilinx Core Generator Tool to achieve the required high speed serial data transmission by using of Aurora 8b/10b Protocol & Multi-Gigabit Transceivers present in Virtex-7 FPGA. Firstly, a 192-bit parallel data is generated using simulators, which is implemented using VHDL language. The 192-bit data is sent to Asynchronous First-In First-Out (AFIFO) as input and produces an output of 32-bit parallel data. This data is sent to the aurora module in parallel form as successive frames (i.e. 6 frames, each frame consists of 4 bytes). Finally, the 192-bit parallel data is transmitted to the receiver module serially over fiber optic cable at the rate of 3.125Gbps using architectural features of virtex7 FPGA. Finally, the data is transmitted on dual independent aurora channels and the entire logic will be tested for its complete functionality in standalone mode by porting on to the Virtex-7 FPGA based custom Hardware.

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DOI: https://doi.org/10.17485/ijst%2F2018%2Fv11i23%2F125648