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Investigations on Performance Metrics of FINFET Based 8-Bit Low Power Adder Architectures Implemented using Various Logic Styles


Affiliations
1 Department of Electronics and Communication Engineering, Panimalar Engineering College, Chennai – 600123, Tamil Nadu, India
 

Objectives: To reduce the leakage power dissipation and minimize the propagation delay, a Fin FET based 8-bit adder architecture is constructed. The performance metrics of these structures are calculated over a range of temperatures and are compared with the MOSFET based 8-bit adder architecture. Various logic styles are utilized for constructing the adder. Method/Analysis: A Ripple carry adder structure is employed. The existing adder architecture is constructed using 90nm MOSFET technology. The proposed adder architecture is constructed using 32nm FINFET technology. The various logic styles employed are Complementary Metal-Oxide Semiconductor logic (CMOS), Complementary Pass-Transistor Logic (CPL), Transmission Gate logic (TG) and Gate Diffusion Input logic (GDI). Cadence Virtuoso is used for designing purpose and simulation is performed using Spectre. Findings: Key performance metrics like static power, dynamic power, leakage power, delay and power delay product are calculated. The dynamic power of MOSFET architecture ranges from 7.42μW to 882.6μW. The dynamic power of FINFET architecture ranges from 0.407nW to 156.2nW. The static power (inputs at high logic level) of MOSFET architecture ranges from 0.001μW to 945.76μW. The static power (inputs at high logic level) of Fin FET architecture ranges from 0.725pW to 170.4nW. The static power (inputs at low logic level) of MOSFET architecture ranges from 0.94nW to 1.68mW. The static power (inputs at low logic level) of Fin FET architecture ranges from 0.127pW to 305.3nW. The leakage power (inputs at high logic level) of MOSFET architecture ranges from 1.27nW to 134.7μW. The leakage power (inputs at high logic level) of Fin FET architecture ranges from 0.36pW to 24.77nW. The leakage power (inputs at low logic level) of MOSFET architecture ranges from 0.54nW to 139.9μW. The leakage power (inputs at low logic level) of Fin FET architecture ranges from 0.15nW to 227.6nW. The delay of MOSFET architecture ranges from 0.344μs to 0.46μs. The delay of Fin FET architecture ranges from 0.19μs to 0.28μs. The power delay product of MOSFET architecture ranges from 2.66 to 405.99. The power delay product of Fin FET architecture ranges from 0.83 to 29.67. Novelty/Improvements: The FINFET adder architecture proved to be effective in reducing the propagation delay and leakage power dissipation. This may find usage in high performance devices like microchips and supercomputers.
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  • Sharma S, Soni G. Comparison analysis of Fin FET based 1-bit full adder cell implemented using different logic styles at 10, 22 and 32nm. International Conference on Energy Efficient Technologies for Sustainability (ICEETS); 2016. p. 660–7. Crossref. PMid:27704370 PMCid: PMC5306072

  • Saraswat R, Akashe S, Babu S. Designing and simulation of full adder cell using FINFET technique. 7th International Conference on Intelligent Systems and Control (ISCO); 2013. p. 261–4. Crossref.

  • Jafari M, Imani M, Ansari M, Fathipour M, Sehatbakhsh N. Design of an ultra-Low Power 32-bit Adder Operating at Sub threshold Voltages in 45-nm Fin FET. 8th International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS); 2013. p. 167–8.

  • Tahrim AA, Tan MLP. Design and Implementation of a 1-bit Fin FET Full Adder Cell for ALU in Sub threshold Region. 2014 IEEE International Conference on Semiconductor Electronics (ICSE 2014); 2014. p. 44–7.

  • Rapolu S, Nikoubin T. Fast and energy efficient Fin FET full adders with cell design methodology (CDM). 6th International Conference on Computing, Communication and Networking Technologies (ICCCNT); 2015. p.1–5.

  • Abbasalizadeh S, Forouzandeh B. Full adder design with GDI cell and independent double gate transistor. 20th Iranian Conference on Electrical Engineering (ICEE 2012); 2012. p. 130–4. Crossref.

  • Moshgelani F, Al-Khalili D, Rozon C. Adder circuits using symmetric and asymmetric FinFETs. 2nd International Symposium on Instrumentation and Measurement, Sensor Network and Automation (IMSNA); 2013. p. 23–6. Crossref.


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  • Investigations on Performance Metrics of FINFET Based 8-Bit Low Power Adder Architectures Implemented using Various Logic Styles

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Authors

M. Aalelai Vendhan
Department of Electronics and Communication Engineering, Panimalar Engineering College, Chennai – 600123, Tamil Nadu, India
S. Deepa
Department of Electronics and Communication Engineering, Panimalar Engineering College, Chennai – 600123, Tamil Nadu, India

Abstract


Objectives: To reduce the leakage power dissipation and minimize the propagation delay, a Fin FET based 8-bit adder architecture is constructed. The performance metrics of these structures are calculated over a range of temperatures and are compared with the MOSFET based 8-bit adder architecture. Various logic styles are utilized for constructing the adder. Method/Analysis: A Ripple carry adder structure is employed. The existing adder architecture is constructed using 90nm MOSFET technology. The proposed adder architecture is constructed using 32nm FINFET technology. The various logic styles employed are Complementary Metal-Oxide Semiconductor logic (CMOS), Complementary Pass-Transistor Logic (CPL), Transmission Gate logic (TG) and Gate Diffusion Input logic (GDI). Cadence Virtuoso is used for designing purpose and simulation is performed using Spectre. Findings: Key performance metrics like static power, dynamic power, leakage power, delay and power delay product are calculated. The dynamic power of MOSFET architecture ranges from 7.42μW to 882.6μW. The dynamic power of FINFET architecture ranges from 0.407nW to 156.2nW. The static power (inputs at high logic level) of MOSFET architecture ranges from 0.001μW to 945.76μW. The static power (inputs at high logic level) of Fin FET architecture ranges from 0.725pW to 170.4nW. The static power (inputs at low logic level) of MOSFET architecture ranges from 0.94nW to 1.68mW. The static power (inputs at low logic level) of Fin FET architecture ranges from 0.127pW to 305.3nW. The leakage power (inputs at high logic level) of MOSFET architecture ranges from 1.27nW to 134.7μW. The leakage power (inputs at high logic level) of Fin FET architecture ranges from 0.36pW to 24.77nW. The leakage power (inputs at low logic level) of MOSFET architecture ranges from 0.54nW to 139.9μW. The leakage power (inputs at low logic level) of Fin FET architecture ranges from 0.15nW to 227.6nW. The delay of MOSFET architecture ranges from 0.344μs to 0.46μs. The delay of Fin FET architecture ranges from 0.19μs to 0.28μs. The power delay product of MOSFET architecture ranges from 2.66 to 405.99. The power delay product of Fin FET architecture ranges from 0.83 to 29.67. Novelty/Improvements: The FINFET adder architecture proved to be effective in reducing the propagation delay and leakage power dissipation. This may find usage in high performance devices like microchips and supercomputers.

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DOI: https://doi.org/10.17485/ijst%2F2018%2Fv11i24%2F111071