Design of Signal Delay-Detection System by using Dual-Edge Trigger Flip Flops

Background: The conventional edge triggered flip-flops usually sample a data signal which is synchronizing with single clock edge. If any noise signal presents around the clock edge, then flip-flops result in malfunction. Methods: This research work presents the design mechanism of Signal Delay Detection System using Dual Edge Trigger Flip Flop (DETFF) which detects the delay occurs in the system and rectifies it to avoid the data loss. Dual Edge Trigger (DET) mechanism maintains the same throughput along with half of clock frequency when compared to the Single Edge Trigger (SET) mechanism. In conventional SET flip flops the sampling of data is done in synchronous with either rising or falling edge of clock since noise can occur across the clock edge which may results in malfunction of data signal. Findings: This problem is resolved by using DETFF as it samples the data at both rising and falling edges respectively with synchronous to clock signal. The DETFF is known for optimizing the noise in the systems by preventing the noise signal generated from different sources which in turn reduces the delay in the system. A new DETFF is proposed in order to improve the sampling capacity of the flip flop so that better optimization of delays can be achieved. Conclusion: This Proposed DET flip flop results in 42% of increment in size but improves the driving capability of flip flop, the operating speed is improved by 27% and 5% of reduction in power consumption.