Dynamic Logic ALU Design with Reduced Switching Power

Background: The dynamic gates produce an extremely high power overhead due to their high switching activity if used in designing a compact and high speed circuit. This paper presents a dynamic logic basedarithmetic and logical unit that can realize reduced switching power to alleviate such a problem. Methods: This is achieved by employingthe modified dual VT domino logic and Limited Switch Dynamic Logic (LSDL) mechanisms. The LSDL technique provides a static like switching action which exhibits lesser area requirement and high speed performance. Findings: The design of the arithmetic and logical units using the conventional dynamic logic, modified dual VT domino logic and the limited switch dynamic logic are presented in the paper for validating the claim. Conclusion: Thesimulation results depict the fact that the use of the LSDL shows 52.86%reduction in the dynamic power in comparison with the conventional dynamic logic. The circuits are implemented using Cadence® Virtuoso tools and 45nm technology node library files. The power analyses are performed using Cadence® Virtuoso Spectre tool.