Low Complexity DWT Architecture Implementation for Feature Extraction using Different Multipliers

Background/Objectives: Discrete wavelet Transform (DWT) is substantially applied in many Digital Signal Processing (DSP) applications. Multiplication of the coefficient is the key factor for complexity in FIR filters. Methods/Statistical Analysis: This paper presents different multiplication techniques used to reduce the complexity in DWT such as Constant Shift Method (CSM), Vedic multiplication and Binary Signed Sub-coefficient (BSS) method. CSM technique uses Shift and Add unit followed with Mux to select appropriate output. BSS technique uses signed sub-coefficients, which reduces the multiplexer size. Vedic multiplication is famous for its low complexity architecture of bit-bit multiplication. Partial product and BCSE methods are used for designing the architectures. The coefficients are represented in IEEE 754 floating point half precision standard. Software simulation is performed in ModelSim and the designs are synthesized in Cadence RC tool for 180 nm technology. Findings: The CSM method gives high speed operation because of its reduced number of adders. The Vedic method provides low power and high speed operation. The BSS method uses Multiplexers and signed bit as control switch, which has a great impact over area requirement. The area requirement is reduced by 6% in BSS technique. Vedic multiplier gives about 23% power reduction compared to conventional multiplier. Both CSM and BSS techniques can be called Reconfigurable architectures as they can be hardwired and the mux output depends on the coefficients only. Conclusion/Improvements: CSM technique is gives the perfect balance for power reduction and area efficiency. Vedic technique gives immense reduction in power consumption but the area overhead is increased.