Design and Implementation of Low-Power, Area-Efficient Fir Filter using Different Distributed Arithmetic Techniques

Background: Distributed Arithmetic (DA) technique is a bit serial operation used to perform vector to vector multiplication in convolution, which is an essential operation in digital filters. This paper presents realization of Finite Impulse Response (FIR) filters using six different DA techniques namely conventional DA, Modified DA (MDA), Offset Binary Coding DA (OBC-DA), Offset Binary Coding Modified DA (OBC-MDA) and LUT-Less DA. Methods: A novel DA method is also introduced which is a combination of multiplexers and Look-Up-Tables (LUT). In DA based FIR filter architecture the partial products of the FIR filter coefficients are pre-calculated and stored in LUTs. The filtering operation is done by shift-accumulation unit. Findings: The designs are simulated using Xilinx ISE and synthesized in Cadence RC using 180-nm technology library. From synthesis reports, it is found that for 4-tap FIR filter, Modified DA consumes 30% less power and 40% less area, whereas for 8-tap FIR filter the saving in power consumption is 30-80% and 35-80% in area. Conclusion: Compared to all the DA techniques mentioned, MDA requires least area and least power consumption because of its less memory requirement. All architectures are designed for 4-tap and 8-tap FIR filters.