FPGA Implementation of Decoder Architectures for High Throughput Irregular LDPC Codes

Objective: VLSI implementation of Decoder Architecture for high throughput using LDPC codes. Methods/Analysis: In this paper, the VLSI architecture of layered partial parallel soft decoding algorithm based decoder for different code size is presented. Findings: LDPC codes provide remarkable error detection performance. Proposed decoder is well matched for VLSI implementation and it is implemented on Xilinx FPGA family. LDPC codes are well-known linear block codes. The computational complexity of LDPC codes is very high as compared to other existing codes like Convolutional codes and Turbo codes. The major benefit is that they offer an enhanced performance, which is very close to the Shannon’s capacity for many different channels and complex algorithms for decoding Novelty/Improvement: By using layered partial parallel soft decoding algorithm, we proposed a pipelined structure that is helpful to achieve higher throughput. The proposed architecture is implemented and tested on FPGA Virtex-5 family with device as 5XC5VLX85. The decoder can attain a throughput of 1.5 Gbps with reduced hardware resources.