FPGA based Green Digital Clock Design for Network Synchronization using LVCMOS I/O Standard

The idea is to develop a green digital clock design that consumes least amount of power for its network specific operation. Low Voltage complementary metal oxide semiconductor i.e. LVCMOS IO standard is used at fixed temperature and changing output load at various frequencies. FPGA family used is Virtex-6 and software used of simulation of proposed algorithm for digital clock is Xilinx. Coding is done using Verilog. The results are taken for LVCMOS at frequency of 0.1GHz, 1GHz, 10GHz and 100 GHz and data is collected to prove it green digital clock. For making any device green means the amount of power consumed by it should be small with desirable output. There is 89.60%, 98.56%, 99.46% and 99.56% saving in IOs power when we reduce output load from 5000pF to 500pF, 50pF, 5pF and 0.5pF respectively.