Modified Architecture for Binary Array Multiplier with Reduced Delay using Tristate Buffers

In VLSI design of system configuration, among the three important parameters of speed, area and power, the speed is purely determined by the delay of the design. In the delay of the design the design delay is contributed by gate delay and routing i.e. path delay. Nowadays in the design, the path or routing delay dominates more towards the design delay compare to the earlier days where gate delay dominates more towards the design delay. Because of scaling in the design, it is essential to concentrate more towards routing delay of the design to get the optimized delay or desired speed of the design with the reduced area. In this work, by studying different architectures constructed with different basic module for binary array multiplier contributes towards the routing delay which can be realized to result in reduced delay.