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A Review on Security in Cache Memories


Affiliations
1 School of Computing, SASTRA University, Thanjavur – 613401, Tamil Nadu, India
 

Objectives: Security in cache memory is a major issue in memory related applications such as smart cards and bio-metric implementations. The objective of this review is to analyze various attacks targeting cache memory and suggest remedial measures to thwart such attacks and assure cache memory security. Methods/Statistical Analysis: Information stored in cache memory can be recovered whenever required. This data is in danger of being hacked by the intruder. Statistical analysis show that attacks such as side channel attacks, timing attacks and power based attacks are adopted to challenge information security in caches. Findings: Discussed solutions involve in the design of secured cryptographic based algorithms, secure aware cache mapping and low power cache design by employing techniques such as code convertors, nested XOR operations, extended Hamming codes and multi-bit clustered ECC. Application/Improvements: Improving and authenticating cache memory security will result in numerous applications involving smart cards and bio-metric applications where secrecy of data is of extreme importance.

Keywords

Cache Memory, Power Based Attacks, Side Channel Attack, Timing Attacks.
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  • A Review on Security in Cache Memories

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Authors

R. Vijay Sai
School of Computing, SASTRA University, Thanjavur – 613401, Tamil Nadu, India
S. Saravanan
School of Computing, SASTRA University, Thanjavur – 613401, Tamil Nadu, India

Abstract


Objectives: Security in cache memory is a major issue in memory related applications such as smart cards and bio-metric implementations. The objective of this review is to analyze various attacks targeting cache memory and suggest remedial measures to thwart such attacks and assure cache memory security. Methods/Statistical Analysis: Information stored in cache memory can be recovered whenever required. This data is in danger of being hacked by the intruder. Statistical analysis show that attacks such as side channel attacks, timing attacks and power based attacks are adopted to challenge information security in caches. Findings: Discussed solutions involve in the design of secured cryptographic based algorithms, secure aware cache mapping and low power cache design by employing techniques such as code convertors, nested XOR operations, extended Hamming codes and multi-bit clustered ECC. Application/Improvements: Improving and authenticating cache memory security will result in numerous applications involving smart cards and bio-metric applications where secrecy of data is of extreme importance.

Keywords


Cache Memory, Power Based Attacks, Side Channel Attack, Timing Attacks.



DOI: https://doi.org/10.17485/ijst%2F2016%2Fv9i48%2F136304