Indian Journal of Science and Technology

The PDF file you selected should load here if your Web browser has a PDF reader plug-in installed (for example, a recent version of Adobe Acrobat Reader).

If you would like more information about how to print, save, and work with PDFs, Highwire Press provides a helpful Frequently Asked Questions about PDFs.

Alternatively, you can download the PDF file directly to your computer, from where it can be opened using a PDF reader. To download the PDF, click the Download link above.

Fullscreen Fullscreen Off


In the VLSI chip designing process, Floor-planning is one of the vital stages which in turn have Placement and Routing tasks. This paper concentrates on solving the problems which occur in VLSI floor planning and gives an overview of placement and routing problems in ICs. This approach depends on recursive optimization prototypes with redefined algorithm. The searching for best solutions is carried out by Genetic Algorithm (GA) on each iteration since these algorithms is already known and proven to solve similar type of problems. GA has been tested randomly and is simulated. By conducting experiments on GA we can realize optimized solutions for the above said problems.

Keywords

Field Programmable Gate Arrays (FPGA) Placement, Genetic Algorithm (GA), VLSI Design.
User