Efficient Implementation of Radix-4 Single pathDelay Feedback (SDF) FFT ProcessorsK

The aim of the current research work is to improve the digital architecture (Radix-4 Single path Delay Feedback) of frequency transformation process. Radix-4 structure reduces the number of steps to half than Radix-2 structure. In the proposed Radix-4 SDF FFT architecture, sequential structures are designed with the help of flip-flops. Traditional FFT structure has complex multiplier architecture to perform the twiddle factor multiplication. But it is not sufficient to large point FFT calculation. Hence, to overcome this problem, Bit Parallel Multiplication (BPM) has been introduced in this paper. In addition, data flow complexity of BPM structures have been realized and re-designed by reducing the most complexity paths. Proposed BPM based twiddle factor multiplier offers 17.5% improvements in area utilization and 7.22% improvements in latency for the value 0.707 and 15.3% improvements in area utilization and 5.97% improvements in latency for the value 0.9238. Proposed Radix-4 SDF FFT offers 47.96% improvements of total latency in Virtex E and 28.02% improvements of total latency in Virtex 6 than traditional Radix-2 SDF FFT. Power consumption of Proposed Radix-4 SDF FFT offers 69.69% improvements in Virtex E and 14.95% improvements in Virtex 6 than traditional Radix-2 SDF FFT. In future, proposed BPM based twiddle factor multiplier will be useful in Orthogonal Frequency Division Multiplexing (OFDM) and Software Defined Radio (SDR) for performing data communication process efficiently.