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In modern technology BIST become pervasive where scan chain plays a major role. An efficient low power BIST method is proposed which occurs in testing. The test set acquires sequence of preprocessed approach inclusive of X-bit 2-D reordering and cube matrix is sequentially distributed. In this paper compression ratio is achieved using MISR. The introduction of MISR and X-masking technique will reduce the compression Ratio. To minimise the repitation of bits MISR plays a vital role. Compression is done by the run length coding and the high compression is achived by the first and second matrix response. MT flling is a method for the replacement technique.CR is calculated using the output values used. The ratio of input bits used to the existing input values which shows the compression ratio. This proposed technique is compared with bench mark circuits s5378, s9234 and s13207 to analyze the area and compression ratio.


Hamming Distance, Multiple Input Scan Register (MISR), X-Masking, Scan Chain.