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Design and Verification of Slave Block in Ethernet Management Interface using UVM


Affiliations
1 VLSI Division, School of Electronics Engineering, VIT University, Vellore - 632014, Tamil Nadu, India
 

Objective:Verification of the Slave block in Ethernet Management Interface using UVM.  Methodology:Management data input output (MDIO) and Management data clock (MDC) is a two-wire interface used by Ethernet Station Management Entity to configure as well as read status from various PHY devices connected to it. Universal verification methodology is used to verify integrated designs. Verification of the Slave block in Ethernet Management Interface is done through UVM. Findings: Verification environment for the Slave Block in Ethernet Management Interface is built using UVM. 94.44% functional coverage and 97.96 code coverage is achieved. Applications: Ethernet protocol is used in the computer communication.


Keywords

Ethernet Management Interface, System Verilog, UVM, Verification
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  • Design and Verification of Slave Block in Ethernet Management Interface using UVM

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Authors

K. Jagannadha Naidu
VLSI Division, School of Electronics Engineering, VIT University, Vellore - 632014, Tamil Nadu, India
M. Srikanth
VLSI Division, School of Electronics Engineering, VIT University, Vellore - 632014, Tamil Nadu, India

Abstract


Objective:Verification of the Slave block in Ethernet Management Interface using UVM.  Methodology:Management data input output (MDIO) and Management data clock (MDC) is a two-wire interface used by Ethernet Station Management Entity to configure as well as read status from various PHY devices connected to it. Universal verification methodology is used to verify integrated designs. Verification of the Slave block in Ethernet Management Interface is done through UVM. Findings: Verification environment for the Slave Block in Ethernet Management Interface is built using UVM. 94.44% functional coverage and 97.96 code coverage is achieved. Applications: Ethernet protocol is used in the computer communication.


Keywords


Ethernet Management Interface, System Verilog, UVM, Verification



DOI: https://doi.org/10.17485/ijst%2F2016%2Fv9i5%2F130648