Implementation of HDB3 Encoder Chip Design

Background/Objectives: Digital communication is the process of transmission of the information which had been encoded digitally at the transmitter side and then passed through the channel encoder followed by the digital decoder at the receiver end. This paper majorly concentrated on low power synthesis and power analysis of HDB3 encoder. Methods: Alternative Mark Inversion (AMI) is a well-known data encoding technique for data encryption. HDB3 encoding is a derivative of AMI (Alternative Mark Inversion) encoding. The HDB3 code is one of the best representation codes which satisfies all the conditions of AMI and improves the limitations of AMI. Findings: The HDB3 encoder is designed with the help of V and B modules. It encodes consecutive zeros by inserting V and B in the form B00V. The VLSI architecture of the HDB3 encoder is implemented in Verilog HDL and the proposed design is synthesized and the results are compared with different TSMC technology libraries. The physical design of the chip is carried out in Cadence SoC Encounter tool. Low power synthesis results shows that the power required for the design is 17.65µW in 45nm technology. Applications: It has the ability to perform functions like Error correction/detection, provides better data encryption techniques in digital communication.