Comparison of Technologies for the Implementation of SBF Decoder for Geometric LDPC Codes

Background/Objectives: The main aim of the proposed design is to optimize the consumption in chip area by improving the error performance by detection and correction. Generally, it is difficult to implement the VLSI based decoding of Geometric LDPC codes because of high complexity and large memory requirements. Methods/Statistical Analysis: In this proposed design architecture we have considered the Soft-Bit Flipping (SBF) algorithm employed here utilizes reliability estimation to improve error performance and it has advantages of Bit Flipping (BF) algorithms. Findings: This proposed design architecture is compared for different technologies using Leonardo spectrum software in Mentor Graphics Tools. We can also obtain the area and delay reports using this tool and optimization of the design is being proposed. Application/Improvement: In future works, this algorithm can be improved with still more security level by having a trade off between performance and data transmission. It can also enhanced by implementing it in real time applications for data decoding and correction, for smaller size datum.