Burrows Wheeler Transform Based Test Vector Compression for Digital Circuits

Background: VLSI testing plays a very crucial role in the design of a VLSI chip. The advances in technology have led to increasing density of transistors and increased circuit complexity in a chip. With the increasing number of inputs, the memory overheads associated with storing test patterns increases. Thus the test pattern volume needs to be compressed. Method: In the proposed approach, a hybrid test pattern compression technique is used along with different schemes such as Huffman and Run length encoding. These encoding schemes are applied on ISCAS’85 and ISCAS’89 benchmark circuits and the results are compared and analyzed based on their compression ratio. Findings: In the proposed approach, an improved compression ratio is obtained when compared to the existing techniques in the literature.