High Vt-low Leakage FDSOI Device for Ultra-low Power Operation

Objectives: The objective of this research paper is to design High Vt-Low Leakage FDSOI Device for Ultra-Low Power Operation. Methods/Analysis: This research work presents the modeling of fully depleted silicon on insulator (FDSOI) device with 350-nm gate length. This paper investigates threshold voltage (Vt) and leakage power of the different FDSOI devices in order to design high threshold voltage and low leakage device. Findings: It is observed that device5 shows higher Vt and dissipates lower leakage power when compared to that of other devices (devices1−4). The threshold voltage and subthreshold slope (SS) of device5 are observed to be 0.199 V (~0.2 V) and 80 mV/decade respectively. The leakage power of the device at drain voltage of 1 V is 41.9 nW. Novelty /Improvement: This kind of FDSOI device is a platform for designing circuits at nano scale regime for ultra-low power applications.