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Improved FPGA Implementation of Real Time Modified Mean Shift Tracking Algorithm


Affiliations
1 Department of Electronics and Communication Engineering, Delhi Technological University, Delhi, India
 

Objectives: To modify and implement color based mean shift object detection and tracking algorithm utilizing both the parallel and sequential capabilities of Xilinx ZYNQ ZC-702 SoC in order to speed up tracking. Method/ Statistical Analysis: The parallel and sequential processing capabilities of Field Programmable Logic Array (FPGA) and Processing System (PS) respectively are utilized in order to have a standalone system that can be faster, reliable and efficient while tracking the object in real time. Operations such as reading and writing video, grabbing kernel from frame and mean shift vector computation are sequential in nature and are best suited for processing system where as the operations parallel in nature are best fit for FPGA and may include estimation of histogram, computation of weights and estimation of weighted histogram. Executing them in parallel helps in reducing the machine cycles and enhances the fps. Findings: The high computational power of the algorithm is met by collective use of hardware and software while keeping the resources available on FPGA in check. The modified mean shift tracking method helps in exploiting the parallel computation capability of the FPGA. The paper compares the results with various techniques implemented on different embedded boards and the frame processing rate is much better with proposed FPGA implementation of modified mean shift tracking algorithm. Further, the window size can be varied without affecting fps. Application/Improvements: The frame rate achieved by using both hardware and software simultaneously is considerably higher than achieved with earlier implementations.

Keywords

Hardware/Software, Hardware Implementation (FPGA), Mean Shift, Real Time.
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  • Improved FPGA Implementation of Real Time Modified Mean Shift Tracking Algorithm

Abstract Views: 164  |  PDF Views: 0

Authors

Rajesh Rohilla
Department of Electronics and Communication Engineering, Delhi Technological University, Delhi, India
Rajiv Kapoor
Department of Electronics and Communication Engineering, Delhi Technological University, Delhi, India

Abstract


Objectives: To modify and implement color based mean shift object detection and tracking algorithm utilizing both the parallel and sequential capabilities of Xilinx ZYNQ ZC-702 SoC in order to speed up tracking. Method/ Statistical Analysis: The parallel and sequential processing capabilities of Field Programmable Logic Array (FPGA) and Processing System (PS) respectively are utilized in order to have a standalone system that can be faster, reliable and efficient while tracking the object in real time. Operations such as reading and writing video, grabbing kernel from frame and mean shift vector computation are sequential in nature and are best suited for processing system where as the operations parallel in nature are best fit for FPGA and may include estimation of histogram, computation of weights and estimation of weighted histogram. Executing them in parallel helps in reducing the machine cycles and enhances the fps. Findings: The high computational power of the algorithm is met by collective use of hardware and software while keeping the resources available on FPGA in check. The modified mean shift tracking method helps in exploiting the parallel computation capability of the FPGA. The paper compares the results with various techniques implemented on different embedded boards and the frame processing rate is much better with proposed FPGA implementation of modified mean shift tracking algorithm. Further, the window size can be varied without affecting fps. Application/Improvements: The frame rate achieved by using both hardware and software simultaneously is considerably higher than achieved with earlier implementations.

Keywords


Hardware/Software, Hardware Implementation (FPGA), Mean Shift, Real Time.



DOI: https://doi.org/10.17485/ijst%2F2016%2Fv9i39%2F126509