Study and Design Evaluation of RF CMOS Oscillators

Objectives: To design and analyze the performance of CMOS RF Oscillator circuits at low supply voltage. Methods/Statistical Analysis: The Current Mode Logic (CML) based oscillator and LC oscillator is designed for 5GHz WLAN applications. The CML design adopts a DCO topology and the schematic layout is drawn using Microwind 2.7. The performance analysis is carried out using Intel Core2 Duo CPU E7400 @ 2.80 GHz processor. Advanced Design System 9.0 is used to implement schematics for analyzing the performances of proposed LC tank oscillator. Findings: The simulated results show that the tri-state inverter based DCO has 20 to 30% power reduction which is more than other conventional oscillator circuits. The CML inverter based DCO consumed more power than tri-state inverter because it used tail current transistor that provides always the static path from supply to ground. The theoretical phase noise is compared with simulated value of –95.19 dBc/Hz at same offset frequency. Application/Improvements: These designs produce a substantial improvement in performance and may be easily integrated with RF front-end blocks with minimal interface problems.