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An Efficient Architecture of Intra Prediction and TQ/IQIT Module of Video Encoder


Affiliations
1 Department of Rail Electrical System, Woosong University, Deajeon, South Korea
 

Objectives: In this paper, an efficient architecture of intra prediction module of H.264 high profile encoder is proposed. This module can be operated in 308 cycles for one macroblock. Methods/Statistical Analysis: The plane mode removal and SAD (Sum of Absolute Difference) distortion calculation are adopted to reduce the hardware cost and cycle. The sharing method of the Q (Quantization) and IQ (Inverse Quantization) modules for I4MB and I8MB prediction, calculation method of the DC value of I16MB and chroma predictions in prediction cycles to speed up the macroblock processing cycle are proposed. Findings: The proposed hardware was verified with the vector generated by reference C using JM13.2. The designed circuit has 250 K gate counts by using TSMC 0.18 um process including SRAM memory and can operate in 160 MHz clock. Improvements/Applications: The cycle for one macroblock is reduced compared with other architectures.

Keywords

High Profile, Integer Transform, Intra-Prediction, Inverse Integer Transforms, Inverse Quantization, Quantization.
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  • An Efficient Architecture of Intra Prediction and TQ/IQIT Module of Video Encoder

Abstract Views: 146  |  PDF Views: 0

Authors

Kibum Suh
Department of Rail Electrical System, Woosong University, Deajeon, South Korea

Abstract


Objectives: In this paper, an efficient architecture of intra prediction module of H.264 high profile encoder is proposed. This module can be operated in 308 cycles for one macroblock. Methods/Statistical Analysis: The plane mode removal and SAD (Sum of Absolute Difference) distortion calculation are adopted to reduce the hardware cost and cycle. The sharing method of the Q (Quantization) and IQ (Inverse Quantization) modules for I4MB and I8MB prediction, calculation method of the DC value of I16MB and chroma predictions in prediction cycles to speed up the macroblock processing cycle are proposed. Findings: The proposed hardware was verified with the vector generated by reference C using JM13.2. The designed circuit has 250 K gate counts by using TSMC 0.18 um process including SRAM memory and can operate in 160 MHz clock. Improvements/Applications: The cycle for one macroblock is reduced compared with other architectures.

Keywords


High Profile, Integer Transform, Intra-Prediction, Inverse Integer Transforms, Inverse Quantization, Quantization.



DOI: https://doi.org/10.17485/ijst%2F2016%2Fv9i43%2F123667