Low Leakage Power Vedic Multiplier using Standard Cell Design

The work proposed in this paper is to reduce the leakage power by using Gate Length Biasing (GLB) technique in a Vedic multiplier. The Gate Length Biasing Technique (GLB) is used to reduce the leakage power by increasing the channel length marginally which in turn increases the delay linearly. As the leakage power reduces a small amount of delay increases which can be ignored. Here Gate Length Biasing (GLB) technique is implemented on a standard cell i.e., NOR standard cell. Then the results are compared with GLB and without GLB. The standard cell with GLB is implemented on digital circuit for application purpose. The digital circuit in which the NOR standard cell is implemented is the 8x8 bit Vedic multiplier. The leakage power with Gate Length Biasing is found to be lesser than the leakage power without gate length biasing technique.