Indian Journal of Science and Technology

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Cascaded H-bridge multilevel inverter structure allows modularized circuit layout and packaging, but they are prone to high switching losses due to high switching frequency. This problem can be alleviated by reducing the number of semiconductor switches and decreasing the number of switching per cycle. To overcome the foresaid drawbacks, this paper presents an 11 level cascaded H-bridge inverter feeding RL load, with reduced switching losses and less harmonic distortion. The inverter output voltage can be shaped by having unequal voltage sources. With proper switching, number of levels can be increased thus reducing the harmonic distortion, meanwhile the number of switching are also to be optimized. The proposed asymmetrical H-bridge inverter uses lesser number of switches and switching.

Keywords

Cascaded Multilevel Inverter, Harmonic Reduction
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