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Keerthana, R.
- Automatic Intelligent Home Appliance Control System
Abstract Views :289 |
PDF Views:3
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Affiliations
1 ECE, P. A. College of Engineering and Technology, Pollachi, IN
1 ECE, P. A. College of Engineering and Technology, Pollachi, IN
Source
Artificial Intelligent Systems and Machine Learning, Vol 7, No 3 (2015), Pagination: 88-90Abstract
The popularity of home automation has been increasing greatly in recent years due to much higher affordability and simplicity through various available technologies. A home automation system integrates electrical devices in a house with each other. The main goal of automation is to reduce human effort and save power. The proposed technique is based on controlling the equipments by measuring the parameters of motion detector, temperature sensor, LDR and smoke sensor. The sensed signals are processed using signal conditioning unit based on the requirements. The microcontroller captures the entire signal and instructs the device to operate accordingly. The electrical equipment like light, fan, refrigerator and alarm are interfaced with microcontroller by suitable drive circuit. The microcontroller also derives an LCD to provide a simple user interface. The master control of the whole circuit lies in operation of magnetic switch which depends on opening and closing of the door.
- Analysis of Current Mode Logic High Speed CMOS Technology
Abstract Views :269 |
PDF Views:2
Authors
Affiliations
1 Department of ECE, Tejaa Shakthi Institute of Technology for Women, Coimbatore, Tamilnadu-641659, IN
1 Department of ECE, Tejaa Shakthi Institute of Technology for Women, Coimbatore, Tamilnadu-641659, IN
Source
Biometrics and Bioinformatics, Vol 10, No 2 (2018), Pagination: 34-36Abstract
We have designed D-latch circuit which is suitable for nanometer technology. The circuit is low-voltage and also high speed. Here we are using Current Mode Logic (CML) technique. This technology is used for improve the speed of the D-latch circuit. We are comparing a two-stage frequency divider designed using both the triple-tail DFF and the proposed folded DFF. During the simulation minimum delay was obtained with the help of proposed folded DFF and it consumes the less amount of power. The delay is reduced and the speed is improved. In the DFF, the maximum operating frequency is achieved over a triple- tail DFF. The simulation is done using cadence virtuoso tool.
Keywords
Current Mode Logic (CML), D–Latch, D–FlipFlop (DFF), Nanometer CMOS.References
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- EMG Signal Detection and Diagnosis of Neuropathy Muscle Disease
Abstract Views :245 |
PDF Views:3
Authors
Affiliations
1 Department of ECE, Tejaa Shakthi Institute of Technology for Women, Coimbatore, Tamilnadu-641659, IN
1 Department of ECE, Tejaa Shakthi Institute of Technology for Women, Coimbatore, Tamilnadu-641659, IN