Informatics Publishing Limited

R. Ganesan

Abstract

Fresh water swamps dominated by Elaeocarpus venustus Bedd. Are one among the many important habitat types of medium elevation evergreen forests in the southern Western Ghats, India. This is yet another important unique habitat type similar to Myristica swamps in the low elevation evergreen forests of Western Ghats.
E. venustus is an endemic plant listed in Red Data book and the habitat is also most threatened due to damming and clearing for plantations in the past. Three types of swamps have been identified based on the distribution of E. venustus and other associated plant species in the swamps. This swampy habitat supports many rare plant species. Trees in the swamps are loaded with various epiphytic plants including orchids compared to the surrounding closed canopy forest. Swamps in the medium devation evergreen forests with E. venustus deserves high priority for conservation as many plants in this unique habitat are rare and endemics.

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B. Imayavathi ¹, V. Karthik ², R. Ganesan ³

Affiliations
1 Electronics and Communication Engineering, Sri Sairam Institute of Technology, Chennai, IN
2 National Engineering College, IN
3 MIT, Anna University, IN

Abstract

Wireless Sensor Networks (WSN) has become a very significant enabling technology in civil, military, radio communication and medical applications for collecting and processing of complex environmental data. Wireless sensor networks have several important attributes that require special attention to device design. These include the need for inexpensive, long-lasting, highly reliable devices coupled with very low performance requirements. Radio communication has highest energy consumption in wireless sensor nodes. Sensor nodes are battery driven and have limited power. Hence, sensor nodes lifetime on the order of months to years. Hence, energy consumption is the important factor in determining sensor nodes lifetime. Power consumption is high during data processing and data transmission process. Inorder to reduce number of data sensed by nodes Data Aggregation is used. Data Aggregation converts multiple sensed data into single data. Here proposing, data aggregation process implemented using DVFS (Dynamic Voltage and Frequency Scaling) algorithm used at input side along with Static Algorithmic Transformation (SAT) uses folded tree architecture to reduce power by reducing number of processing elements and to improve performance of sensor nodes. Experimental results shows that using DVFS algorithm reduces power up to 13% compared to existing processing methods.

Keywords

Folded Tree, DVFS, Processing Elements, WSN.

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P. Kanmani ¹, R. Anitha ², R. Ganesan ²

Affiliations
1 Deparment of Computer Science, Arignar Anna Government Arts College Attur, Salem Dt Tamil Nadu, IN
2 Department of MCA, K. S. Rangasamy College of Technology, Tiruchengode, Namakkal Dt, Tamil Nadu, IN

Abstract

Mobile computing introduces new flexibility such as continuous access to computing resources while the users travel.This facility raises new challenges such as fault tolerance in distributed mobile computing system. In this paper we present a non blocking token ring based checkpointing algorithm to tolerate the faults in the mobile computing environment. It is a single phase algorithm neither having the overhead of temporary checkpoints nor using dependency vector; and also it avoids the avalanche effect. Results shows that it outperforms two-phase algorithms.

Keywords

Checkpointing, Nonblocking, Token Ring.

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J. Jeba Priya ¹, M. Annalakshmi ², R. Ganesan ³

Affiliations
1 Department of VLSI Design, Sethu Institute of Technology, Kariapatti-626106, Tamilnadu, IN
2 Department of ECE, Sethu Institute of Technology, Kariapatti- 626106, Tamilnadu, IN
3 VLSI Design, Sethu Institute of Technology, Kariapatti- 626106, Tamilnadu, IN

Abstract

VLSI architecture of resource efficient the image scaling processor is proposed in this project. The filter combining, hardware sharing, and reconfigurable techniques had been used to reduce hardware cost. This image Scaling Processor consists of a sharpening spatial filter, a clamp filter, bilinear and a nearest neighborhood interpolation. To reduce the blurring and aliasing artifacts produced by the bilinear interpolation, the sharpening spatial and clamp filters are added as prefilters. To minimize the memory buffers and computing resources for the proposed image processor design, a T-model and inversed T-model convolution kernels are created for realizing the sharpening spatial and clamp filters. Compared with previous low-complexity techniques, this architecture requires only a one-line-buffer memory. For achieve more quality images the orthogonal decoder is proposed. This proposed system is designed using verilog HDL, simulated using Modelsim Software and synthesized using Xilinx Project Navigator.

Keywords

Bilinear Interpolation, Clamp Filter, Sharpening Spatial Filter, Reconfigurable Calculation Unit (RCU).

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M. Mohamed Rasik Raja ¹, R. Ganesan ¹

Affiliations
1 Sethu Institute of Technology, Kariapatti, Virudhunagar, Tamilnadu, IN

Abstract

Hough transform is used for detecting circles in an image. To reduce the huge computations in Hough transform, a resource efficient architecture is essential. Resource efficient and reduction in processing time are achieved with data parallelism. We present a circle detection method based on genetic algorithms. Our genetic algorithm uses the encoding of three edge points as the chromosome of candidate circles (x, y, and r) in the edge image of the scene. Fitness function evaluates if these candidate circles are really present in the edge image. Our encoding scheme reduces the search space by avoiding trying unfeasible individuals, this result in a fast circle detector. The implementation of GA-based Hough transform on an FPGA. This architecture is implemented using alter a device at operating frequency of 200MHz. It compute the Hough transform of 512×512 test images with 180 orientation in 2.05 to 3.15ms with minimum number of FPGA resources.

Keywords

Edge Detection, Circle Detection, Genetic Algorithm, Circle Objects Recognition, Mat Lab, Xilinx.

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R. Ganesan ¹, A. Arul Lawrence Selvakumar ¹

Affiliations
1 Adhiparasakthi Engineering College, IN

Abstract

Conventional authentication schemes allow a serviceable server to authenticate the legitimacy of a remote login user. However, these schemes are not used for multi-server architecture environments. This paper presents a secure and efficient remote user authentication scheme for multi-server environments.

This user authentication scheme is a pattern classification system based on an artificial neural network. In this scheme, the users only remember user identity and password to log in to various servers. Users can freely choose their password. Furthermore, the system is not required to maintain a verification table and can withstand the replay attack.

Keywords

Neural Network, Multi Server Architecture, User Authentication, Remote Login, Security.

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P. Kanmani ¹, R. Anitha ², R. Ganesan ³

Affiliations
1 Department of Computer Science, Arignar Anna Government Arts College, Attur, Salem Dt. Tamil Nadu, IN
2 Department of MCA, K. S. Rangasamy College of Technology, Tiruchengode, Namakkal Dt, Tamil Nadu, IN
3 Department of MCA, K. S. Rangasamy College of Technology, Tiruchengode, Namakkal Dt, Tamil Nadu, IN

Abstract

Mobile computing introduces new flexibility such as continuous access to computing resources while the users travel.This facility raises new challenges such as fault tolerance in distributed mobile computing system. In this paper we present a non blocking token ring based checkpointing algorithm to tolerate the faults in the mobile computing environment. It is a single phase algorithm neither having the overhead of temporary checkpoints nor using dependency vector; and also it avoids the avalanche effect. Results shows that it outperforms two-phase algorithms.

Keywords

Checkpointing, Nonblocking and Token Ring.

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R. Ganesan ¹, K. Vivekanandan ²

Affiliations
1 Department of Computer Science, Coimbatore, IN
2 Govt. College of Technology, IN

Abstract

Internet banking has made it easy to carry out the personal or business financial transaction without going to bank and at any suitable time. This facility enables to transfer money to other accounts and checking current balance alongside the status of any financial transaction made in the account. However, in order to maintain privacy and to avoid any misuse of transactions, it is necessary to follow a secured architecture model which ensures the privacy and integrity of the transactions and provides confidence on internet banking is stable. In this research paper, a secured hybrid architecture model for the internet banking using Hyper elliptic curve cryptosystem and MD5 is described. This hybrid model is implemented with the hyper elliptic curve cryptosystem and it performs the encryption and decryption processes in an efficient way merely with an 80-bit key size. The various screen shots given in this contribution shows that the hybrid model which encompasses HECC and MD5 can be considered in the internet banking environment to enrich the privacy and integrity of the sensitive data transmitted between the clients and the application server.

Keywords

E-Banking, Hyperelliptic Curve Cryptosystem, MD5, Authentication, Confidentiality, Integrity, Nonrepudiation, Privacy.

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R. Ganesan ¹, S. Pradeep ¹, R. Sinthuja ¹, T. Vithya ¹

Affiliations
1 Bharathiyar College of Engineering & Technology, Karaikal, U.T. of Puducherry, IN

Abstract

Existing traffic control system is using sensors. As the sensor which collects traffic flow information, mainly Ultrasonic Vehicle Detector has been used. This detector detects vehicle presence by the time difference of the reflection of ultrasonic wave fired from above the road surface to just under it. But especially queue and delay length are measured indirectly by the number of passed vehicles in a unit time. So a sensor which can collect more precise traffic flow information is needed. Also each Ultrasonic Vehicle Detector has to be installed above the road surface per a measurement lane and so there is a fear of spoiling the beauty of the city. On the other hand, the Digital Image processes an image received from the CCTV camera installed aside and above the approach lane at the traffic signal intersection. In this, queue length will be detected. To detect and measure queue parameters, two different algorithms have been used. The first algorithm is motion detection and the second is a vehicle detection operation. In this process, we detect moving vehicle grouping and delay vehicle grouping from the results of Image Preprocess, and calculate the delay range. Also, we make a stable output which is strong in the noise by smoothing the calculated delay range by referring to the output at the time of back and forth. After the queue length detection, depend upon the vehicles in four sides the preference will give to the vehicles. This saves the time and reduces the error in the existing system.

Keywords

Ultrasonic Vehicle Detector, Motion Detection, Vehicle Detection, Queue Length Parameters.

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S. Karthick Raja ¹, R. Ganesan ²

Affiliations
1 Alagappa University, Karaikudi,Tamilnadu, IN
2 Department of M.E-VLSI Design at Sethu Institute of Technology, IN

Abstract

A novel algebraic integer (AI) based multien- coding of Daubechies-12 2-D wavelet filters having error-free integer-based computation. Digital VLSI architectures empl- oying parallel channels are proposed, physically realized and tested. The multi-encoded AI framework allows a multiplication-free and computationally accurate architect- ture. It also guarantees a noise-free computation throughput the multi-level multi-rate 2-D filtering operation. A single final reconstruction step (FRS) furnishes filtered and down-sampled image outputs in fixed-point, resulting in low levels of quantization noise. Daubechies-12 designs in terms of SNR, PSNR, hardware structure and power consumptions, for different word lengths are compared to Daubechies-12 and -6. SNR and PSNR improvements of approximately 41% were observed in favors of AI-based systems, when compared to 8-bit fixed-point schemes (six fractional bits). Further, FRS designs based on canonical signed digit representation and on expansion factors are proposed. The Daubechies-12 4-level VLSI architectures are prototyped on a Xilinx Virtex-6 vcx240t-1ff1156 FPGA device at 282 MHz and 146 MHz, respectively, with dynamic power consumption of 164 mW and 339 mW, respectively, and verified on FPGA chip using an ML605 platform.

Keywords

Algebraic Integer Encoding, Daubechies Wavelets, Error-Free Algorithm, Fixed-Point Scheme, Sub-Band Coding, VLSI.

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R. Cauvery ¹, B. Muthupandian ², R. Ganesan ³

Affiliations
1 VLSI Design from Sethu Institute of Technology, Anna University, Chennai, IN
2 Department of ECE Design, Sethu Institute of Technology, IN
3 Department of M.E-VLSI Design at Sethu Institute of Technology, IN

Abstract

Todays emerging technology is to integrate the electronic device which arises memory fault in system and also occupy more space. Here, proposed that Finite state machine based soft memory repair strategy to reduced access time, lesser occupancy of circuit board and lower power consumption. Linear-Density Parity-Check (LDPC) decoder was used in architecture to provide acceptable error tolerance, and implement of an orthogonal frequency-division multiplexing (OFDM) system as measured by the Bit Error Rate (BER) and the Packet Error Rate (PER). The proposed memory strategy was improved at 0.52 dB gain.

Keywords

Interleaver, Orthogonal Frequency-Division Multiplexing Receiver, Finite State Machine, Soft Memory Repair, System-On-Chip.

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R. Ganesan ¹, S. Radhakrishnan ²

Affiliations
1 Department of EIE, RVS College of Engineering, Dindigul, TamilNadu, IN
2 Department of CSE, Kalasalingam University, Srivilliputhur, TamilNadu, IN

Abstract

In this paper a new method for texture classification of CT scan brain images based on Gray Level Run Length Method (GLRLM) is proposed. Other two conventional methods, Spatial Gray Level Dependency Method (SGLDM), and standard Gray Level Run-Length Method (GLRLM) are used to compare the performance of the proposed method. The feature vector consists of 14 Haralick features. The proposed algorithm applied to real time CT scan images. We achieved the classification rate 88% in the distinction between normal and abnormal images. Based on our experiments, the Reduced Gray Level Run Length Method (RGLRLM) is more appropriate than other methods for texture classification as it leads to higher classification accuracy.

Keywords

Brain Classification, Feature Extraction, Neural Network and Texture Analysis.

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R. Ganesan ¹, K. Vivekanandan ²

Affiliations
1 Department of Computer Science and Applications, PSG College of Arts & Science, Tamil Nadu, IN
2 Bharathiar School of Management and Entrepreneur Development, Bharathiar University, Tamil Nadu, IN

Abstract

The performance analysis of Hyperelliptic Curve Cryptosystems (HECC) over prime fields (Fp) of genus 5 and 6 are discussed in this paper. We have implemented a HECC system of genus 5&6 in a Intel Pentium III Celeron Processor @ 933 MHz speed with 256 MB RAM in Java 1.5. We have also compared their efficiency on the parameters of time taken for divisor generation, key generation, encryption and decryption. Our results demonstrate that the performance of higher genus HECC system gets degraded in terms of divisor generation, key generation, encryption and decryption process.

Keywords

HECC, Finite Field, Genus, Divisor Generation, Key Generation, Encryption, Decryption.

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George Thomas ¹, Bhanu Pant ¹, R. Ganesan ¹, V. Ramachandra ¹, R. Vasudevan ²

Affiliations
1 Vikram Sarabhai Space Centre, Trivandrum, IN
2 Indian Institute of Technology, Madras, IN

Abstract

The resulting microstructure and mechanical properties of Ti-6A1-4V alloy depend to a great extent on the temperature at which working is carried out. Two components namely 650mm diameter Rings and 650mm diameter Hemispherical Shells have been processed at temperatures about 50°C below and 100°C above the beta-transus temperature respectively. These components have been evaluated for their microstructures, mechanical 'properties, fracture toughness and weldability. The microstructure of the rings which have been rolled at 950°C reveals the presence of equiaxed primary alpha in the matrix of transformed beta. On the other hand, the microstructure in the case of hemispherical shells forged at 1100°C, is 100 percent transformed beta. The tensile ductility of the rings is found to be higher than that of the hemispherical shells. However, the fracture toughness of hemispherical shells is much superior to the rings. The samples cut from these components are machined to 12mm thickness and electron beam welded for their comparative property evaluation. It is seen that the welded samples reflect and retain almost the same tensile properties as the parent material except for the impact toughness at the fusion zones.

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