Refine your search
Collections
Co-Authors
Journals
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z All
Gomathi, P.
- An Empirical Analysis of the Profitability of Indian Oil Refineries
Abstract Views :139 |
PDF Views:4
Authors
Source
International Journal of Innovative Research and Development, Vol 2, No 2 (2013), Pagination: 500-523Abstract
It can be inferred from the study that operating efficiency of selected oil refineries in India was satisfactory and the management generally succeeded in investing capital funds. The performance of Reliance Industries Ltd and Chennai Petroleum Corporation Ltd was good during the study period. Mangalore Refinery Petrochemicals Ltd and Essar Oil Ltd have not performed well during the period of study. Further, owner's funds were utilized profitably by all the selected oil refineries in India except Mangalore Refinery and Petrochemicals Ltd and Essar Oil Ltd. It is significant to note that the position regarding earnings per share and dividend payout ratio in all the selected oil refineries during the period under review shows better performance and prospects from the point of view of shareholders. The results showed that Hindustan Petroleum Corporation Ltd, Bharat Petroleum Corporation Ltd, Mangalore Refinery and Petrochemicals, Essar Oil Ltd and Reliance Industries Ltd experienced a strong tendency in profitability to decline over the study period. The falling tendency of profit rate of these companies is the proof of adverse effect of various controls on process, output, expansion, investment and distribution imposed by government on these companies over time. Only in the case of Mangalore Refinery and Petrochemicals Ltd, Chennai Petroleum Corporation Ltd and Reliance Industries Ltd, the time trend co-efficient is positive implying the tendency of profit rate to rise over time. The study concluded that the analysis of profitability of the selected oil refineries reveals that majority of the companies under review highlighted better performance and prospects from the point of view of owners.Keywords
Profitability, Indian Oil Refinery, Profitability Trend, Return on Capital Employed, Solvency, Debt-equity Ratio and Earnings per ShareFull Text
- Design and Implementation of FIR Filter Architecture using High Level Transformation Techniques
Abstract Views :195 |
PDF Views:0
Authors
Affiliations
1 Electronics and Communication Engineering, M. Kumarasamy College of Engineering, Karur, Thalavapalayam – 639113, Tamil Nadu, IN
1 Electronics and Communication Engineering, M. Kumarasamy College of Engineering, Karur, Thalavapalayam – 639113, Tamil Nadu, IN
Source
Indian Journal of Science and Technology, Vol 11, No 17 (2018), Pagination:Abstract
Objectives: FIR filter structure is designed with area and delay optimization is designed using Systolic Architecture and Associativity High Level Transformation technique in this paper. Finite Impulse Response (FIR) filter structure with optimized parameters is one of the major challenges in VLSI Signal Processing. Methods/Statistical Analysis: The designed FIR filter is designed using Modelsim for functionality verification and the structure is implemented in Spartan 3E FPGA kit using Xilinx ISE simulator for the analysis of the designed architecture. Findings: The FIR filter is designed with 4-Tap, 8-Tap and 16-Tap length and the designed architecture using Systolic architecture with Associativity technique shows 8.9%, 2.3% and 2.4% reduction in LUT for 4-Tap,8-Tap and 16-Tap filter respectively and 14.22%,11.89% and 12.32% reduction in delay for 4-Tap,8-Tap and 16-Tap filter respectively. Application/Improvements: Further Associativity techniques may be used for future work.Keywords
Architecture, FIR Filter, High Level TransformationFull Text
- Segmentation and Extraction of Chromosomes from G-Band Metaphase Images
Abstract Views :192 |
PDF Views:0
Authors
Affiliations
1 Department of Electronics and Communication Engineering, M. Kumarasamy College of Engineering, Karur, Thalavapalayam – 639113, Tamil Nadu, IN
1 Department of Electronics and Communication Engineering, M. Kumarasamy College of Engineering, Karur, Thalavapalayam – 639113, Tamil Nadu, IN
Source
Indian Journal of Science and Technology, Vol 11, No 18 (2018), Pagination:Abstract
Objectives: Genetic problems can be identified by a test called Karyotyping. Karyotyping is used to find the abnormalities and genetic disorders or defects. The automated segmentation and disentangling of chromosomes are the challenging issues. Methods/Statistical Analysis: In current systems the separation between touching and overlapping chromosomes need human intervention. Different procedures are proposed to obtain the chromosome from its background. In this paper, an attempt is made to separate the chromosomes for Karyotyping in G-Band metaphase images. As a first step segmentation of chromosomes is done. Findings: Thesis carried out by means of local thresholding, region growing and edge detection methods. Then, the chromosome and its clusters are extracted by labelling the connected components. This process successfully separates individual chromosomes. Application: Medical image Processing.Keywords
Chromosome Analysis, Edge Detection, Image Segmentation, Karyotyping, Region GrowingFull Text
- Power Quality Improvement in Power System Using Multilevel Inverter under Non Linear Load Condition
Abstract Views :200 |
PDF Views:1
Authors
Affiliations
1 Department of Electrical and Electronics Engineering, N.S.N. College of Engineering and Technology, Karur, IN
1 Department of Electrical and Electronics Engineering, N.S.N. College of Engineering and Technology, Karur, IN
Source
Digital Signal Processing, Vol 10, No 5 (2018), Pagination: 83-85Abstract
The multilevel inverter reduces the harmonic contents and achieves sinusoidal signals. The hybrid active filter to achieve power quality compensation and active power filter with low power rating is used to filter the other higher order harmonics and power factor can also be improved. Almost near to unity with the help of shunt capacitors this system helps to improve the electrical supply quality. A Multilevel Inverter (MLI) is a power electronic device built to produce a desired A.C voltage from several levels of DC voltages.
Generally unbalanced voltages will occur at supply side these can be eliminated by using multi-level Inverter. Hence increase the efficiency of the system if the system stability problems or power quality issues which needs to be resolved and limited utilization and they operate at relatively low power level with respect to the designed power rating during most of long-term field operations High temperature peaks and variations on switching devices due to the intermittency which accelerates the degradation of the switching devices. To tackle the overloading issue, this system therefore proposes a hybrid power control concept with the objective to improve the system performance and increase the power factor of multilevel inverter and hence MATLAB simulation have been carried out.
Keywords
Multilevel Inverter, Higher Order Harmonics, Hybrid Power Control.
References
- I. Mahendravarman, A. Ragavendiran, S. Preethi, “A New Soft Switching Scheme for Power Factor Correction In UpsBasedApplication” Nov 2014
- Ninujoy, Mohammed Jouhar, KeerthiSabu, Mari Philip“Harmonic Reduction and Power Factor Improvement in Ups”June-2016
- P.Adhityan, M.Rajkumar, M.R.Neetu Singh,“Improvement Of Power Quality Using Cascaded Multilevel Inverter In T-Statcom Based System” June-2015
- NanditaVenugobal, Saipriya Ramesh, N.ShanmugaVadivu,”Modified Approach for Harmonic Reduction in Multilevel Inverter” Nov 2012
- Mr.Y.Prakash, Dr.S.Sankar, “Power Quality Improvement Using Dvr in Power System”Aug- 2014
- B.Harish, U.RajaKiran, B.Madan Lal1, Soubhagya Kumar Dash, “Power Quality Improvement of Dc-Ac Converter by Using Cascaded H-Bridge Multilevel Inverter”Feb-2014
- Prof. Pravin G. Dhawale, Prof. Sandip S. Godhade, “Power Quality Improvement of Hybrid System Using Active Control Methods”Jan-2017
- Vasanthakumar, K.Ramcharan, “Power Quality Improvement Using 3 Phase Cascaded H-Bridge Multi Level Inverter under Unbalanced Voltage Conditions”July-2012
- IonelVechiu, Etxeberria, QuentinTabart, “Power Quality Improvement Using an Advanced Control of A Four-Leg Multilevel Converter” Jan-2014
- N.Chelammal, SubhransuSekar Dash, Velmurugan“Power Quality Improvement Using Multilevel Inverter as Series Active Filter”May-2012
- Adiabatic Logic Based Power Efficient Multiplexer
Abstract Views :262 |
PDF Views:0
Authors
Affiliations
1 Department of ECE, M. Kumarasamy College of Engineering, Karur, Tamil Nadu, IN
1 Department of ECE, M. Kumarasamy College of Engineering, Karur, Tamil Nadu, IN
Source
International Journal of Emerging Trends in Science & Technology, Vol 4, No 1 (2018), Pagination: 8-13Abstract
This paper gives low power answers for VLSI. Power utilization of CMOS is quickly turning into a noteworthy worry in VLSI outline. Through adiabatic method dynamic power utilization in pull up system can be decreased and vitality put away on the heap capacitance can be reused. In this paper distinctive rationale style multiplexes have been dissected and low power 2:1 multiplexer is outlined utilizing positive criticism adiabatic rationale. It has been watched that adiabatic multiplexer devours 53.1% less power than vitality conserved pass-transistor (EEPL) multiplexer. An adiabatic compressor has been planned utilizing PFAL rationale, which has indicated 79% change than ordinary CMOS compressor as far as power. Every one of the reproductions are completed by Microwind 3.1 apparatus.Keywords
CMOS, VLSI.References
- H. E. Chang, J. D. Huang, and C. I. Chen “Input selection encoding for low power multiplexer tree,” IEEE Conference on VLSI Design Automation and Test, pp. 1-4, 2007.
- S. Kim, C. H. Ziesler, and M. C. Papaefthymiou, “Charge-recovery computing on silicon,” IEEE Transactions on Computers, vol. 54, no. 6, pp. 651-659, June 2005.
- S. M. Kang, and Y. Leblebici, “CMOS digital integrated circuits: Analysis and design,” Tata Mcgraw-Hill, 2003
- Y. Takahashi, Y. Fukuta, T. Sekine, and M. Yokoyama, “2PADCL: Two Phase drive adiabatic dynamic CMOS logic,” IEEE Conference on Circuits and Systems, pp. 1484-1487, 2006.
- L. Wang, J. Hu, and H. Li, “Adiabatic tree multipliers using modified booth algorithm,” IEEE Conference on ASIC, pp. 161-164, October 2007.
- C. H. Chang, J. Gu, and M. Zhang, “Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits,” IEEE Transactions on Circuits and Systems, vol. 51, no. 1, pp. 1985-1997, October 2004.
- M. Padmaja, and V. N. V. S. Prakash, “Design of a multiplexer in multiple logic styles for low power VLSI,” International Journal of Computer Trends and Technology, vol. 3, no. 3, pp. 467-471, 2012.
- I. Gupta, N. Arora, and B. P. Singh, “Analysis of several 2:1 multiplexer circuits at 90nm and 45nm technologies,” International Journal of Scientific and Research Publications, vol. 2, no. 2, pp. 1-6, February 2012.
- I. Gupta, N. Arora, and B. P. Singh, “An efficient design of 2:1 multiplexer and its application in 1-bit full adder cell,” International Journal of Computer Application and Its Application in 1 Bit Full Adder, vol. 40, no. 2, pp. 31-36, February 2012.
- G. L. Madhumati, M. Madhavilatha, and K. R. Rao, “Power and delay analysis of a 2-to-1 multiplexer im plemented in multiple logic styles for multiplexer-based decoder in flash ADC,” International Journal of Recent Trends in Engineering, vol. 1, no. 4, pp. 29-31, May 2009.
- R. Zimmermann, and W. Fichtner, “Low-power logic styles: CMOS versus pass-transistor logic,” IEEE Journal of Solid-State Circuits, vol. 32, no. 7, pp. 1079-1090, July 1997.
- M. Song, G. Rang, S. Kim, and B. Kang, “Design methodology for high speed and low power digital circuits with energy economized pass-transistor logic (EEPL),” IEEE Conference on Solid State and Circuits, pp. 120-123, 1996.
- N. Tzartzanis, and W. C. Athas, “Clock-powered CMOS: A hybrid adiabatic logic style for energy-efficient computing,” IEEE Conference Circuits and Systems, pp. 137-151, 1999.
- M. Arsalan, and M. Shams, “Charge-recovery power clock generators for adiabatic logic circuits,” IEEE Conference on Embedded System Designs, pp. 171-174, 2005.
- V. S. K. Bhaaskaran, “Energy recovery performance of quasi-adiabatic circuits using lower technology nodes,” IEEE Conference on Power Electronics, pp. 1-7, 2011.
- M. Chanda, P. Sil, R. Mitra, A. Dandapat and H. Rahaman, “Comparative analysis of adiabatic compressor circuits for ultra-low power DSP application,” International Conference on Advances in Recent Technologies in Communication and Computing, pp. 355-359, 2010.
- N. Weste, and K. Eshraghian, Principles of CMOS VLSI design: A system perspective reading, Pearson Education: Addison-Wesley, 2002.
- E. Sicard, and S. D. Bendhia, Basic of CMOS Cell design, Tata Mc Graw-Hill, 2005.
- E. Sicard, and S. D. Bendhia, Advance of CMOS Cell design, Tata Mc Graw-Hill, 2007.