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Nandal, Amita
- Booth Multiplier Using Reversible Logic with Low Power and Reduced Logical Complexity
Authors
1 Department of ECE, NIT Hamirpur-177005, Himachal Pradesh, IN
2 School of Electronics Engineering, VIT University, Chennai-600127, Tamil Nadu, IN
Source
Indian Journal of Science and Technology, Vol 7, No 4 (2014), Pagination: 525-529Abstract
The proposed testable reversible architecture scheme yields significantly reduced complexity, low power and high speed features. It is a key issue in the interface of computation and physics, and of growing importance as miniaturization progresses towards its physical limits. With the advent of nanotechnology the fault detection and testability is of high interest for accuracy. This research work describes the reversible testable design of high-speed modified Booth multipliers. The proposed multiplier circuits are based on the modified Booth algorithm can be used to accelerate the multiplication speed with reduced power consumption. The resultant multiplier circuit shows better performance than others and can be used in the systems requiring very high performance. The proposed booth multiplier design shows 12% reduced logical complexity, 10% reduced power consumption and efficient device utilization achieved in comparison to existing reversible logic.Keywords
Barrel Shifter, Booth Encoding, Booth Multiplier, Logical Complexity, Partial Products, Reversible Gate And Testability- An Efficient Barrel Shifter Design Using Testable Reversible Logic
Authors
1 Electronics and Communication Department, SRM University, Chennai, IN
Source
Programmable Device Circuits and Systems, Vol 3, No 8 (2011), Pagination: 396-401Abstract
Data shifting is required in many key computer operations from address decoding to computer arithmetic. With the advent of quantum computer and reversible logic, the design and implementation of all devices in this logic has received more attention. The various operations like arithmetic and logical operations, address decoding and indexing etc., require data shifting and rotating. For high speed applications the barrel shifters become more popular which can shift and rotate multiple bits in a single cycle. In this research work, a reversible barrel shifter structure, computation delay and power consumption is presented which outperforms the conventional design. The experimental result shows that the proposed reversible barrel shifter has 5% higher speed and 10% power efficient as a single unit when compared to the conventional barrel shifter design.
Keywords
Barrel Shifter, Multiplexer, New Gate, New Testable Gate, Reversible Logic and Testability.- An Efficient Canonical Signed Digit Multiplier Design for Image Processing Applications
Authors
1 Electronics and Communication Department, SRM University, Chennai, IN