Programmable Device Circuits and Systems

Abhi Gondaliya ¹, Jayesh Popat ¹

Affiliations
1 Department of Electronics and Communication Engineering, Marwadi Education Foundation, Rajkot-360003, IN

Abstract

In recent days, the importance of security in the information technology has increased significantly. Advance Encryption Standard (AES), a Federal Information Processing Standard (FIPS), is a cryptographic algorithm that can be used to protect electronic data. With the increasing demand for secure transaction in banking and other such system, encryption and decryption using cryptography algorithm which play a very important role. Nowadays, Most secure transactions occurring on smart phones, commercial uses and other hand-held devices, a low on chip area and a high speed algorithm to perform the same become the need for recent days. In order to achieve higher performance in today's heavily loaded communication networks, hardware implementation is a wide choice in terms of better speed and reliability. In This Review paper present the various hardware Architecture of Advance Encryption standard (AES) algorithm using Xilinx Vertex XCV1000BG560-4 Field Programmable Gate Array (FPGA).

Keywords

Various Architecture of Advance Encryption Standard (Aes), Fpga.

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Abhi Gondaliya , Jayesh Popat

Abstract

In recent days, the importance of security in IT sectors has been increased significantly. Advanced Encryption Standard (AES), is an approved cryptographic algorithm that can be used to protect electronic data. Nowadays, Most of secure transactions are occurring on smart phones, ATM transactions and other handheld devices. So that high speed algorithm to perform the same has become the need for recent days. For high speed performance in algorithm and to reduce unbreakable delay in combinational path then pipeline architecture is used. So that proposed work employs a s-box design based on pipeline Architecture synthesis and simulated on Modelsim Altera and also implemented on Altera DE-2 board. So this architecture employs a Boolean simplification of the truth table of the logic function with the aim of reducing the critical path. .The S-Box is designed using basic gates such as AND gate, NOT gate, OR gate and multiplexer. After designing of s-box based on pipeline architecture then critical path has been decreased and also increased in throughput

Keywords

Advance Encryption Standard (AES), S-Box, Combinational Logic, Pipeline, FPGA

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