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Hardware-Friendly Vision Algorithm Using FPGA Embedded I/O Resources
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With the advent of mobile embedded multimedia devices that are required to perform a range of multimedia tasks, especially image processing tasks, the need to design efficient and high performance image processing systems in a short time-to-market schedule needs to be addressed. Image Processing algorithms implemented in hardware have emerged as the most viable solution for improving the performance of image processing systems. A single-chip FPGA implementation of a vision core is an efficient way to design fast and compact embedded vision systems from the PCB design level. The scope of the project is to design a novel FPGA-based parallel architecture for embedded vision entirely with on-chip FPGA resources. Block-RAMs and IO interfaces are used for the design. As a result, the system is compact, fast and flexible. Architectures for several mid-level neighbourhood algorithms are designed using Xilinx Sparton 3E FPGA. The algorithm uses a vision core which supports image processing on a low-resolution image. The simulation results are compared with existing FPGA implementations. The performance of the algorithms could be substantially improved by applying sufficient parallelism.
Keywords
FPGA, Parallel Processing, Pipeline Processing, Real Time, Vision System.
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