Networking and Communication Engineering

S. V. Viraktamath ¹, G. V. Attimarad ², Prakash R. Tonse ¹

Affiliations
1 ECE Department, S.D.M.C.E.T, Dharwad, Karnataka, IN
2 ECE Department, D.S. College of Engineering, Bangalore, Karnataka, IN

Abstract

Convolutional Coding and Decoding (CODEC) is a Forward Error Correction (FEC) technique that is particularly suited for a channel in which the transmitted signal is corrupted mainly by Additive White Gaussian Noise (AWGN). The Viterbi Algorithm (VA) has been widely applied for decoding convolutionally encoded data in digital communication systems over the last 30 years. In this proposed work, the hardware implementation of Flexible Adaptive Viterbi (FAV) Decoder is discussed. For a given code, the proposed algorithm yields nearly the same error performance as the Viterbi Algorithm while requiring a substantially smaller average number of computations. For the selected design parameters of code rate = ½ and constraint length of 3, a working frequency as high as 323.520MHz is observed on implementing FAV design on Xilinx Spartan 3e Field Programmable Gate Array (FPGA). Description of the Viterbi algorithm, design methodology of implementing it in VHDL (Very High Speed Integrated Circuits Hardware Description Language) and final implementation results using Xilinx ISE software are also given.

Keywords

Adaptive Viterbi, Convolutional, FEC, Trellis.

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