Design and Optimization Via Graphical Optimization Method of an Injection-Locked Frequency Divider in 0.35 μm Process

This paper proposes a wide tuning Injection-Locked Frequency Divider (ILFD) and describes its operation principle. The circuit is made of a differential CMOS-tank oscillator in 0.35 μm process and is based on the direct injection topology. A theoretical prediction of the Locking range is developed and a graphical optimization of the circuit is done. The simulated results obtained with optimum parameter sizing show that at 2.5 V supply voltage, the divider free-running frequencies are from 2.27 to 2.53 GHz. The locking range of the proposed ILFD is about 548 MHz from the incident frequency 4.524 to 5.074 GHz. The power consumption is 9 mW and the phase noise of the locked output is -128.6 dBc/Hz at 1 MHz offset frequency.