Digital Image Processing

Khyati S. Borad ¹, Jaikaran Singh ¹, Mukesh Tiwari ¹

Affiliations
1 Sri Satya Sai Institute of Science and Technology, Sehore, Bhopal, IN

Abstract

H.264 video compression standard gives high coding efficiency, but requires a significant amount of complexity and power utilization. This paper presents an Area Efficient and high performance architecture for H.264 baseline profile entropy encoder and also presents advanced low-power algorithms for an H.264 encoder and a power-aware design composed of low-power and area efficient algorithms. In the proposed design, an efficient methods are used to design exp-golomb and CAVLC to reduce the hardware cost. The proposed hardware design of H.264 encoder operates at 100 Mhz clock frequency. the logic element  count of the proposed design is 1557.

Keywords

FPGA, VHDL, ALTERA Quartus II, Exp-Golomb, CAVLC, Code_Num.

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