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Sakthivel, R.
- Tourism Managers Competency A Critical Evaluation on Kerala Tourism
Authors
1 Bharathiar University, Coimbatore Tamil Nadu, IN
2 No Affiliation
3 Department of Management Studies, Toc H Institute of Science and Technology Kochi, Kerala, IN
Source
Journal of Strategic Human Resource Management, Vol 3, No 1 (2014), Pagination: 31-39Abstract
The robust growth of tourism industry was quite satisfactory even in the toughest macroeconomic environment across the globe. Nearly 85 percent countries have reported positive growth and out of this 33 percent have recorded double digit growth. The travel and tourism industry holds tremendous potential for contributing to the Indian economy also. The Government of Kerala, by way of an aggressive marketing strategy has envisaged the achievement of a yearly growth rate of fifteen percent on foreign tourist arrivals and seven percent on domestic tourist arrivals respectively. Despite the sluggishness in targeted market, tourism operators are putting all efforts to attract tourists with innovative marketing techniques to achieve the envisaged target. Though the Government of Kerala has taken so many initiatives to reduce the gap in the man power requirement, this could not be achieved. Attrition rate of this industry has not only been causing a dent on the performance of existing staff but it has an adverse effect also in the tourism sector as a whole. Keeping this in view, a questionnaire survey was conducted among the professionalsassociated with tourism industry to find out the competency needs of tourism managers who can perform and meet the target in this dynamic environment. The data was subjected to statistical analysis and found the various generic and functional competencies that are required for managing the tourism industry effectively.Keywords
Competency Model, Generic Competency, Technical Competency, Kerala Tourism
- A Novel Approach for Identifying Expired Products Using Bar Code Scanner
Authors
1 CK College of Engineering and Technology, Cuddalore, IN
Source
Software Engineering, Vol 8, No 2 (2016), Pagination: 35-38Abstract
Supermarket is the place where consumers come to purchase their daily using products and pay for that. Now a days there are lots of expired products present in the market and Authentication is one of the most important processes for any consumer or customer to identify whether the product is within the limit of its expiry date. In our existing system there is no barcodes only manual entry of a product is done for billing or inventory system so customer have to wait long in line for their purchases to be processed. Then later barcode scanning is introduced for billing it provides fast access about the product price and discounts by scanning but it doesn’t provide the Product expiry date validation. In our proposed system, expiry date of the product is verified by a bar code scanner to avoid the unnecessary selling of expired products in retail shops, medicals, and supermarket. It controls the billing system to prevent from expired products added on bill or invoice.
Keywords
Bar Code Scanning, Billing System, Expiry Date Validation, Inventory Management.- A Novel AES VLSI Architecture with Fully-Sub Pipelined Structure for High Throughput and Area Efficiency
Authors
1 School of Electronics Engineering, VIT University, IN
2 School of Electrical Engineering, VIT University, IN
3 School of Information and Technology, VIT, IN
Source
Programmable Device Circuits and Systems, Vol 1, No 7 (2009), Pagination: 183-188Abstract
This paper presents novel high-speed architectures for the hardware implementation of the Advanced Encryption Standard (AES) algorithm. Unlike previous works which rely on look-up tables to implement the SubBytes and InvSubBytes transformations of the AES algorithm, the proposed design employs combinational logic only. As a direct consequence, the unbreakable delay incurred by look-up tables in the conventional approaches is eliminated, and the advantage of subpipelining can be further explored. Furthermore,composite field arithmetic is employed to reduce the area requirements, and different implementations for the inversion in subfield (24) are compared. The subkeys, required for each round of the Rijndael algorithm, are generated in real-time by the keyscheduler module by expanding the initial secret key, thus reducing the amount of storage for buffering. Moreover, a novel architecture was proposed for the fully sub-pipelining is used after each standard round, and sub-pipelined with in the round states, so throughput was increased double to any pipelined architecture. This AES design was implemented using Verilog HDL and synthesized using TSMC’s 90 nm standard cell library with RTL Compiler, and physical design implementation was done using SOC Encounter and achieved the through put of 38. 4 Gbps after detailed routing.
Keywords
AES Algorithm, Sub-Pipeline, VLSI, Lookup-Table.- Low Leakage Power Vedic Multiplier using Standard Cell Design
Authors
1 School of Electronics Engineering, Vellore - 632014, Tamil Nadu, IN
2 School of Information and Technology, Vellore - 632014, Tamil Nadu, IN
Source
Indian Journal of Science and Technology, Vol 8, No 24 (2015), Pagination:Abstract
The work proposed in this paper is to reduce the leakage power by using Gate Length Biasing (GLB) technique in a Vedic multiplier. The Gate Length Biasing Technique (GLB) is used to reduce the leakage power by increasing the channel length marginally which in turn increases the delay linearly. As the leakage power reduces a small amount of delay increases which can be ignored. Here Gate Length Biasing (GLB) technique is implemented on a standard cell i.e., NOR standard cell. Then the results are compared with GLB and without GLB. The standard cell with GLB is implemented on digital circuit for application purpose. The digital circuit in which the NOR standard cell is implemented is the 8x8 bit Vedic multiplier. The leakage power with Gate Length Biasing is found to be lesser than the leakage power without gate length biasing technique.Keywords
Gate Length Biasing Technique, Leakage Power, Standard Cell, Vedic MultiplierFull Text
- VLSI Architecture for Image Contrast Enhancement using Modified Adaptive Gamma Correction with Weighting Distribution
Authors
1 VIT University, Vellore – 632014, Tamil Nadu, IN
Source
Indian Journal of Science and Technology, Vol 9, No 5 (2016), Pagination:Abstract
Background/Objectives: Due to the huge volume of data involved, it is very much challenging to design efficient contrast enhancement algorithms in real time applications. In this paper an efficient hardware is presented for image enhancement. Methods/Statistical analysis: The computation algorithms are based on the calculations of image Probability Density Function (PDF) and Cumulative Distribution Function (CDF). For better results weighted PDF and smoothed CDF computations are performed. Then the adaptive gamma correction is used for enhancing the image contrast. A compensated CDF is used as the adaptive gamma parameter. To reduce hardware complexity, approximation techniques are employed. In the modified algorithm, the bi-histogram equalization is utilized. Xilinx system generator is used for hardware co-simulation. The hardware is implemented on an FPGA based 'Zed Board'. Findings: The hardware oriented method achieves similar quality image as the software approach and the results are qualitatively and quantitatively analyzed. The PDF and CDF based computations are faster than other image processing methods. So this algorithm is suitable for real time applications. The image is found to have a better quality in the modified AGCWD method. The PSNR value also is found to be better than the normal method. But the hardware utilization of the modified algorithms is found to be higher than the normal algorithm. The bi-histogram approach is suitable to preserve the mean brightness of the original image. Applications/Improvements: Future works may modify the proposed method, for reducing the hardware requirements. Contrast enhancement is one of the crucial image processing techniques in high definition image and video applications. Image enhancement techniques find applications in LED and LCD display processing, medical image analysis etc.Keywords
Adaptive Gamma Correction, Contrast Enhancement, Histogram Modification, Weighting Distribution, Zed BoardFull Text
- Low Power Realization of Subthreshold Digital Logic Circuits using Body Bias Technique
Authors
1 VLSI Division, School of Electronics Engineering, VIT University, Vellore - 632014, Tamil Nadu, IN
Source
Indian Journal of Science and Technology, Vol 9, No 5 (2016), Pagination:Abstract
Background/Objectives: As technology scaling down, subthreshold operation is playing a vital role in the design of digital circuits to achieve ultra low power consumption with considerable performance. Methods/Statistical Analysis:This paper presents a novel body bias technique, where the body terminal of NMOS is reverse biased to VDD which reduces the subthreshold leakage. The basic logic gates are designed using proposed body bias scheme. To analyze the performance, standard 28 transistor full adder cell is implemented using the proposed technique and the performance parameters - power, delay, PDP are calculated and compared with the conventional CMOS Full adder. The simulations are done in cadence 90 nm technology for VDD = 0.2v. Findings: The simulation results show that the circuits designed using the proposed technique achieves more than 31% savings in power and more than 15% savings in PDP than traditional body bias technique used in static CMOS configuration. Applications/Improvements: These circuits are widely applicable in portable battery operated devices such as cellular phones, wearable electronics and remote sensors where ultra low power consumption is required with low to medium performance.Keywords
Body Bias, CMOS, Full Adder, Logic Gates, Subthreshold Operation, Ultra Low PowerFull Text
- Low - Power and Area - Efficient Square – Root Carry Select Adders using Modified XOR Gate
Authors
1 VLSI Division, School of Electronics Engineering, VIT University, Vellore - 632014, Tamil Nadu, IN
Source
Indian Journal of Science and Technology, Vol 9, No 5 (2016), Pagination:Abstract
Background/Objectives: XOR gate is a primary element in binary adders because which is used to detect sum – output. In this paper a 2-input XOR gate is accomplished by a modified design. Methods/Statistical analysis: Usually a half adder (HA) circuit is designed with one XOR and one AND gate but if this modified XOR is used in HA, the design requires only one XOR gate and the AND gate can be acquired from XOR gate itself. Findings: This modified XOR gate design gives better result when the adder circuit has more number of XOR gates, so we used this modified XOR gate in conventional sqrt CSLA, binary to excess-1 converter (BEC) based sqrt CSLA and optimized logic based (OLB) sqrt CSLA. The results show that Area – Delay – Product (ADP) has been reduced in proposed circuits, 12.45% in conventional sqrt CSLA, 21.45% in BEC based sqrt CSLA and 17.81% in OLB sqrt CSLA. Applications/Improvements: These adders can be used in Arithmetic Logic Unit (ALU) of a micro-processor as a binary adder.
Keywords
Application Specific Integrated Circuits (ASIC), Area Efficient, Low Power, Sqrt CSLA, XOR GateFull Text
- Consumers Buying Preference of Mobile Network Service Providers with Special Reference to Salem City, Tamil Nadu
Authors
1 Karpagam University, Coimbatore - 641021 Tamil Nadu, IN
2 Government Arts College, Coimbatore-641018 Tamil Nadu, IN
Source
Asian Journal of Management, Vol 3, No 3 (2012), Pagination: 158-162Abstract
The implementation of LPG developed the India by the foreign company's entry. In India the mobile telecommunication network service increased considerably and it plays second largest network role in the world. In the competition market the Mobile network service providers grow and survive only through service quality and fulfilling the several highly developed features at cheapest price. The mobile network customers giving more importance to several factors before subscribing the network to get the best one so the study aims to examine the customer's satisfaction towards mobile network service providers.Keywords
Consumer Buying Preference, Mobile Network Service, Satisfaction Level.- Smart Trolley for Medication and Health Care
Authors
1 Department of Electrical and Electronics Engineering, KPR Institute of Engineering and Technology, Coimbatore, Tamilnadu, IN
Source
Automation and Autonomous Systems, Vol 9, No 4 (2017), Pagination: 78-81Abstract
The proposed model is designed to provide a better service for patients, kids and aged people. It consists of a trolley provided with DC Geared Motors which is controlled through an Android Application. This makes the aged person or the needy partially independent. The model is built with Arduino Uno Controller, Bluetooth module (BCM92073X_LE_KIT) and a suitable Android Application. The heart of the proposed work is Arduino Uno Controller which controls the geared DC motors through L298D driver. The trolley is designed with a buzzer which beeps, once the destination is reached. In case of any obstacle on the path or an individual, again there's a beep and continues to move towards the destination after the individual is passed. The trolley will return back in the travelled path after a fixed time of service. The metal mounted on the ground decides the path for the trolley to travel. The operation provided being a simple one, a child can also operate this module, initiating a better quality tech based service. This design can also be used in hospitals that make the people independent to get the needs of patient time to time.Keywords
Arduino, Trolley, Automation, Proximity Inductive Sensor.- Extinction of the Elixir of Life: Depletion of Groundwater Level In Chennai
Authors
1 School of Hotel and Catering Management, Vels Institute of Science Technology and Advanced Studies (VISTAS), Pallavaram, Chennai, IN
Source
Indian Journal of Public Health Research & Development, Vol 10, No 11 (2019), Pagination: 1233-1238Abstract
Orientation: There has been a growing unease in depletion of ground water in Chennai due to the increase industrial population, creating difficulties in day to day operation of hotels.
Research purpose: To list out the problems with regard to water scarcity faced hotels in and around the areas of Chennai. Exhibit the practices and procedures followed by the hotels in overcome these problems.
Motivation for the study: Currently the city is facing a major water scarcity problem which is due to climatic changes, over consumption of ground water supply, lack of water saving activities etc. Hotel industries being a prime user of groundwater exerts a principal role in depleting the groundwater hereby has the responsibility in rescheduling the water conserve practices.
Research design, approach and method: A qualitative and quantitative study has been done in twenty three hotels located in and around Chennai with a well designed questionnaire as the research tool.
Findings: Presently no well planed practices or policies exist in water management at hotel industries. Still many hotels have not implemented water conservation initiatives to save groundwater. Awareness has to be created among the managements, employees and guest to minimise the water crisis.