Amita Nandal ¹, T. Vigneswaran ², Ashwani K. Rana ¹

Affiliations
1 Department of ECE, NIT Hamirpur-177005, Himachal Pradesh, IN
2 School of Electronics Engineering, VIT University, Chennai-600127, Tamil Nadu, IN

Abstract

The proposed testable reversible architecture scheme yields significantly reduced complexity, low power and high speed features. It is a key issue in the interface of computation and physics, and of growing importance as miniaturization progresses towards its physical limits. With the advent of nanotechnology the fault detection and testability is of high interest for accuracy. This research work describes the reversible testable design of high-speed modified Booth multipliers. The proposed multiplier circuits are based on the modified Booth algorithm can be used to accelerate the multiplication speed with reduced power consumption. The resultant multiplier circuit shows better performance than others and can be used in the systems requiring very high performance. The proposed booth multiplier design shows 12% reduced logical complexity, 10% reduced power consumption and efficient device utilization achieved in comparison to existing reversible logic.

Keywords

Barrel Shifter, Booth Encoding, Booth Multiplier, Logical Complexity, Partial Products, Reversible Gate And Testability

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S. Nirmalraj ¹, T. Vigneswaran ²

Affiliations
1 Department of E.E.E, Sathyabama University, IN
2 Department of E.C.E, VIT University, Chennai, IN

Abstract

Background: All natural signals are subjected to sparsity when they are properly represented by a basis function. Sparsity helps us to sample the signals less than Nyquist rate which clearly explained by the recent theory known as compressive sensing. Methods: This paper explains that DFT does a good job in converting the given image into sparse when the energy density of the image is varied and also a cascaded transform DFT and DWT is proposed. Qualitative measures for the cascaded transform were observed to be good. Result: It helps us to convert a given image signal into sparse without loss in information content present in that image. Application: While converting an analog signal into digital, sparsity will help to compress a given analog signal before conversion. So the number of samples obtained by sampling the compressed signal becomes less.

Keywords

Compressive Sensing, Energy Density, Image Transforms Information Preservation Capability, Sparsity.

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E. Chitra ¹, T. Vigneswaran ²

Affiliations
1 Department of Electronics and Communication Engineering, SRM University, Kanttankulathur - 603203, Tamil Nadu, IN
2 School of Electronics Engineering, VIT University, Chennai Campus, Chennai - 600127, Tamil Nadu, IN

Abstract

Background/Objectives: FIR filters play a vital role in signal processing applications. This research work presents a low power and high speed efficient buffer based Distributed Algorithms and it is analyzed with Electro Cardio Gram (ECG) signal Finite Impulse Response (FIR) filter design. Methods/Statistical Analysis: The proposed FIR filter is designed using buffer based DA and it is simulated and synthesized using Cadence digital labs. This is compared with different architectures such as conventional DA, separated look up table DA and LUT less DA. Findings: Synthesis report shows that the proposed design has 52% less power dissipation compared with the conventional DA, 21% reduction in delay with separated Look Up Table (LUT) DA and 8% reduction in area with LUT less DA. Conclusion/Improvements: Presently this method is applied for ECG signal input with 16-tap FIR filter. This can be extended for higher order filters to achieve better performance.

Keywords

Distributed Arithmetic (DA), Electro Cardio Gram (ECG), Finite Impulse Response (FIR), Look Up Table (LUT)

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V. Sarada ¹, T. Vigneswaran ²

Affiliations
1 Department of ECE, SRM University, Chennai - 603203, Tamil Nadu, IN
2 School of Electronics Engineering, VIT University, Chennai - 632014, Tamil Nadu, IN

Abstract

Objectives: This paper proposes a design of Low power FFT (Fast Fourier Transform) processor used in OFDM (Orthogonal Frequency Division Multiplexing) application as there is demand for low power design of portable communication device. Methods: This FFT processor is based on SDF (Single Path Delay Feedback) pipelined Architecture. Digit slicing multiplier less architecture aids in realizing the complex Multiplication. To reduce power dynamic power dissipation, the proposed architecture applies clock gating buffer. Control circuit is implemented using Gray code sequence instead of binary code sequence. The design proposed here is implemented in Verilog HDL. Cadence tool is used for synthesizing the proposed design Findings: The number of complex multiplication is also reduced by using radix -25 algorithms. The result shows reduced power consumption up to 25%. Improvements: This paper is presented for 64 Point FFT design; this can also be extended for Higher N point FFT design.

Keywords

Clock Gating, FFT, Multiplier Less Multiplier, Radix 25, SDF

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P. T. Thasneem Salim ¹, T. Vigneswaran ¹

Affiliations
1 School of Electronics and Communication Engineering, VIT University, Chennai – 600127, Tamil Nadu, IN

Abstract

Background: The main threat in communication is the unauthorized access of information third party without the knowledge of sender and receiver. Hence the security plays a vital role in data transmission systems. Confidential data like internet banking account passwords and email account passwords needs security in their text data. Data can be text, image, video and audio. Methods: The purpose of this research work is to implement a mechanism to hide information (image) using cryptography. Advanced Encryption Standard (AES) is a type of symmetric cryptography standard which can be used to transfer a block of information securely during transmission. Findings: The idea of this paper is to generate an encrypted image by giving image input to AES encryption system and getting the decrypted image as original image by giving encrypted image as input to the AES decryption system. The input image is given through MATLAB R2012b to ModelSim6.3 and the system simulation and synthesis is done by integrating Model Sim to the Altera DE2 115 board through Quartus II software. Conclusion: The maximum frequency attained from this workis 165.462MHz. Finally image is displayed through an LCD which is connected to the board using Video Graphics Array (VGA) Connector.

Keywords

AES, Cryptography, Decryption, Encryption, Hiding

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Akhilesh Murikipudi ¹, V. Prakash ¹, T. Vigneswaran ¹

Affiliations
1 School of Electronics Engineering, VIT University, Chennai – 600127, Tamil Nadu, IN

Abstract

Background/Objectives: The objective of the paper is to analyze the General Purpose Operation System (GPOS) performance with Real Time Operating System(RTOS) using a mobile robot as a real time application. The mobile robot module is implemented on a single board computer having ARM11 as its core. Methods/Statistical Analysis: The method used to calculate response is realfeel method which uses dedicated timer and interrupt to calculate the response. Findings: The response of the mobile robot is calculated by interrupting the mobile robot with some obstacles. Findings:In addition to this, other parameters such as speed, rotations time and precision resulted by the sensor are also calculated. RTOS have an average of 20μs where as GPOS have an average of 102μs of response time in real time environment.Conclusion:The results show that RTOS has better response time than GPOS. The minimum distance required to stop the mobile robot in RTOS is more accurate than GPOS. Compare to GPOS, the RTOS is able to avoid the obstacle collision even for a shorter distance.

Keywords

GPOS, Latency Calculation, Mobile Robot, Response Time, RTOS, Single Board Computer

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Jonnalagadda Raghavendra ¹, T. Vigneswaran ¹

Affiliations
1 School of Electronics Engineering, VIT University, Chennai - 600127, Tamil Nadu, IN

Abstract

Background: In Digital Signal Processing (DSP) the complex arithmetic instructions are mostly used. The decoding of these instructions usually takes more time in many applications. Methods: The objective of this research work mainly focused on the delay reduction by decreasing the partial products with the help of higher radix booth recoder. The booth recoder plays a key role in fused add-multiply operation for partial product generation. Findings: The proposed fused add multiply unit reduces the delay by reducing the number of partial products which is very useful for fast arithmetic circuits. The fused add-multiply units are simulated in Xilinx® 14.3 ISE in Virtex-5 environment and synthesized in Cadence® RTL Compiler and layout generated from Cadence® Encounter in 180nm technology. Conclusion: Based on experimental results, it is observed that the delay of the proposed method is reduced by 17.5% than the existing work.

Keywords

Accumulate Units, Booth Recorder, Fast Arithmetic, Fused Add Multiply, Multiply

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Madhu Lodhi ¹, T. Vigneswaran ¹

Affiliations
1 School of Electronics Engineering, VIT University, Chennai - 600127, Tamil Nadu, IN

Abstract

Background: The conventional edge triggered flip-flops usually sample a data signal which is synchronizing with single clock edge. If any noise signal presents around the clock edge, then flip-flops result in malfunction. Methods: This research work presents the design mechanism of Signal Delay Detection System using Dual Edge Trigger Flip Flop (DETFF) which detects the delay occurs in the system and rectifies it to avoid the data loss. Dual Edge Trigger (DET) mechanism maintains the same throughput along with half of clock frequency when compared to the Single Edge Trigger (SET) mechanism. In conventional SET flip flops the sampling of data is done in synchronous with either rising or falling edge of clock since noise can occur across the clock edge which may results in malfunction of data signal. Findings: This problem is resolved by using DETFF as it samples the data at both rising and falling edges respectively with synchronous to clock signal. The DETFF is known for optimizing the noise in the systems by preventing the noise signal generated from different sources which in turn reduces the delay in the system. A new DETFF is proposed in order to improve the sampling capacity of the flip flop so that better optimization of delays can be achieved. Conclusion: This Proposed DET flip flop results in 42% of increment in size but improves the driving capability of flip flop, the operating speed is improved by 27% and 5% of reduction in power consumption.

Keywords

Delay Detection Mechanism, Dual Edge Trigger, Flip Flop, Signal Delay.

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