S. Sivanantham ¹, R. Adarsh ¹, S. Bhargav ¹, K. Jagannadha Naidu ¹

Affiliations
1 ASIC Design Laboratory, School of Electronics Engineering, VIT University, Vellore-632014, Tamilnadu, IN

Abstract

Today's mobile networks are moving towards creating base stations and mobile stations that are compatible with many standards simultaneously. One way of achieving it is to reconfigure and time multiplex the processing resources based on the present necessity. Field Programmable Gate Arrays have become one of the best choices for implementing digital signal processing and Software Defined Radio platforms due to advancements in VLSI over the past few decades. Partial Reconfiguration has regained its importance in the last decade and is the one of the best methodologies to implement an Software Defined Radio. This paper presents an implementation of physical layer specifications of IEEE 802.11g using dynamic partial reconfiguration on FPGA. The Orthogonal Frequency Division Multiplexing (OFDM) Physical layer is implemented with various encoding and modulation schemes to achieve different data rates. The design has been implemented in Xilinx Virtex-5 board.

Keywords

FPGA, IEEE 802.11g, OFDM, Partial Reconfiguration

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K. Thilagavathi ¹, S. Sivanantham ¹

Affiliations
1 School of Electronics Engineering, VIT University, Vellore - 632014, Tamil Nadu, IN

Abstract

Objectives: A low-transition Test Pattern Generator (TPG) known as Bit Swapping LFSR (BS-LFSR) which generates the test vectors with low transitions. This will increase the correlation and results in one transition between the consecutive test patterns. Methods: The BS-LFSR comprises of an external XOR type LFSR along with multiplexer. The bit swapped test patterns alone is not enough to reduce the average and peak power. The Weighted Transition Metric (WTM) is calculated after shifting of test patterns into the scan cells. Based on WTM values for each test pattern, scan cells are reordered to reduce the test power. Findings: The various CUTs are chosen from ISCAS 89 standard benchmark circuits. The CUTs are synthesized using RTL Compiler tool from Cadence and the scan chain inserted Gate Level Netlist are obtained for each CUT respectively. Improvements: Experimental results show that power reduction is attained by employing the technique.

Keywords

BIST, LFSR, Scan Chain Reordering, Test Pattern Generator.

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S. Aravind Babu ¹, S. Babu Ramki ¹, S. Sivanantham ¹

Affiliations
1 ASIC Design Laboratory, School of Electronics Engineering, VIT University, Vellore – 632014, Tamil Nadu, IN

Abstract

The direct implementation of parallel particle swarm optimization algorithm on Field Programmable Gate Array (FPGA) is presented in this paper. In the proposed design, the particle unit architecture is independent of fitness unit and hence the particle unit is reusable and flexible for different fitness function. The parallel co-processor implementation of each particle accelerates the execution speed and reduces the operating power as compared to the software execution of the design on a general purpose processor. The proposed implementation reduces the number of registers by 2.76% and the number of look-up-tables by 0.62% on average.

Keywords

Co-processor, FPGA Implementation, Particle Swarm Optimization, Parallel Architecture.

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S. Sivanantham ¹, R. Adarsh ¹, S. Bhargav ¹, K. Jagannadha Naidu ¹

Affiliations
1 ASIC Design Laboratory, School of Electronics Engineering, VIT University, Vellore – 632014, Tamil Nadu, IN

Abstract

Today's mobile networks are moving towards creating base stations and mobile stations that are compatible with many standards simultaneously. One way of achieving it is to reconfigure and time multiplex the processing resources based on the present necessity. Field Programmable Gate Arrays have become one of the best choices for implementing digital signal processing and Software Defined Radio platforms due to advancements in VLSI over the past few decades. Partial Reconfiguration has regained its importance in the last decade and is the one of the best methodologies to implement an Software Defined Radio. This paper presents an implementation of physical layer specifications of IEEE 802.11g using dynamic partial reconfiguration on FPGA. The Orthogonal Frequency Division Multiplexing (OFDM) Physical layer is implemented with various encoding and modulation schemes to achieve different data rates. The design has been implemented in Xilinx Virtex-5 board.

Keywords

FPGA, IEEE 802.11g, OFDM, Partial Reconfiguration.

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Chirag Patel ¹, M. Srikanth ¹, Kalyani Chetan Kumar ¹, S. Sivanantham ¹

Affiliations
1 School of Electronics Engineering, VIT University, Vellore - 632014, Tamil Nadu, IN

Abstract

The OpenCL is a standard parallel language which is based on 'C' language. It offers users to take full advantage and also provide the flexibility of high level language. In this paper, we explore the use of OpenCL language to implement the complex design on FPGAs by describing the design with high level abstraction language. To demonstrate, we consider the most important benchmarks in financial markets known as Monte-Carlo Black-Scholes implementation to estimate the stock price option

Keywords

Embedded Unit, FPGA Implementation, Kernel, Monte-Carlo Simulation, OpenCL Standard.

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