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Bhavani, S.
- An Efficient Secured Localization based Optimized Energy Routing for MANET
Abstract Views :231 |
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Authors
Affiliations
1 Karpagam University, Coimbatore - 641021, Tamil Nadu, IN
2 Department of ECE, Karpagam University, Coimbatore - 641021, Tamil Nadu, IN
1 Karpagam University, Coimbatore - 641021, Tamil Nadu, IN
2 Department of ECE, Karpagam University, Coimbatore - 641021, Tamil Nadu, IN
Source
Indian Journal of Science and Technology, Vol 8, No 35 (2015), Pagination:Abstract
Background/Objectives: Secure Localization is a major issue in MANET which is mainly focusing on keeping confidential information about mobile nodes and data packets. Several approaches have been proposed to obtain location information and node authentication. However, it is some lagging in balancing energy consumption and location authentication. Methods/Statistical Analysis: In this research, location based secure routing is proposed for location authenticity among mobile nodes. It contains three phases. In first phase, multipath route determination. In second phase, reliable nodes are chosen for packet forwarding towards destination node. In third phase, destination with secure location update is determined to secure nodes. Findings: For simulation, the network simulator tool (NS 2.34) is used. Based on the simulation result, the proposed work achieved that secured location authenticity and minimum energy consumption. Applications: This work can be suggested as real time approach in battlefield approach, disaster applications and earthquake issues.Keywords
Energy consumption, Location Update, Location Authenticity and Balancing Energy Consumption, Secure localization- A Novel Paradigm to Eliminate Timing Violations using AHL
Abstract Views :198 |
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Authors
Affiliations
1 Department of ECE, Kumaraguru College of Technology, Coimbatore – 641049, Tamil Nadu, IN
2 Karpagam Academy of Higher Education, Coimbatore - 641021, Tamil Nadu, IN
3 Department of ECE, Karpagam Academy of Higher Education, Coimbatore - 641021, Tamil Nadu, IN
1 Department of ECE, Kumaraguru College of Technology, Coimbatore – 641049, Tamil Nadu, IN
2 Karpagam Academy of Higher Education, Coimbatore - 641021, Tamil Nadu, IN
3 Department of ECE, Karpagam Academy of Higher Education, Coimbatore - 641021, Tamil Nadu, IN
Source
Indian Journal of Science and Technology, Vol 9, No 44 (2016), Pagination:Abstract
Objectives: This Paper presents a novel low power design approach for multipliers to eliminate timing violations. There are two major issues which are concentrated in this paper are positive bias temperature instability and negative bias temperature instability. Both the things affect the speed of transistor and leads to timing violations, which intern leads to the failure of an entire system. Methods: In this work, bypassing multiplier is used with adaptive hold logic. The implementation is done in 180 nm deep submicron CMOS technology. Findings: power consumption and error rate is studied after employing the AHL. Improvements: The experimental result shows that the performance of multipliers with AHL improved 72.8% when compared to existing methods and consumes less power.Keywords
AHL, Bypass Multipliers, Low Power Design, Instability, Timing Violations.- Improving Performance of IQA Algorithm: A Simplified Approach to SSIM based on Image Gradients
Abstract Views :149 |
PDF Views:0
Authors
Affiliations
1 UKF College of Engineering and Technology, Parippally Kollam, Kerala – 691302, IN
2 Departmentof Electronics and Communication Engineering. Karpagam Academy of Higher Education Coimbatore - 641 021,Tamil Nadu, IN
1 UKF College of Engineering and Technology, Parippally Kollam, Kerala – 691302, IN
2 Departmentof Electronics and Communication Engineering. Karpagam Academy of Higher Education Coimbatore - 641 021,Tamil Nadu, IN