R. Sivaraman ¹, R. Parameshwaran ¹

Affiliations
1 School of Computing, SASTRA University, Thanjavur, Tamil Nadu, IN

Abstract

This paper proposes enhanced parallel adder architectures with low power and reduced area. It includes, design of three different parallel adders such as Ripple Carry Adder (RCA), Carry Look ahead Adder (CLA) and Carry Select Adder (CSA). All three adders are designed in Gate Diffusion Interface (GDI) technique as well as traditional CMOS method. Adder is a basic common combinational digital circuit. Adders are important components in signal processing, image and video processing applications. So it is essential to have compact, low power adder design for these application fields. GDI based digital system design offers reduction in power consumption and area over head. When compared to traditional CMOS based design, GDI uses very less transistor to implement a function. The GDI and CMOS methods are taken in to account for the comparison of design parameters such as design layout, node to node delay, total power dissipation and speed of operation. All three parallel adders are designed in traditional CMOS as well as GDI method. The simulations are done using Microwind2 and DSCH2 analysis software tools and the results between those two types are listed below. This proposed adder circuits can be used in all high speed multipliers and filter designs where low power and reduced area is a major concern.

Keywords

Area, Combinational Circuits, Parallel Adders, Digital Design, Power.

Full Text

   

P. Anbarasan ¹, K. Hariharan ¹, R. Parameshwaran ¹

Affiliations
1 School of Computing, SASTRA University, Thanjavur- 613401, Tamil Nadu, IN

Abstract

In this paper, low power low voltage Op-amp which forms the basic building block for various devices is designed by making the transistors of the Op-amp to operate in sub-threshold region. Now-a-days portable electronic devices are of great demand which thereby increases the demand for low power and low voltage design of devices. Conventionally, two stage op-amps are used which requires higher power with comparatively low gain. In order to overcome this, operation of devices in sub-threshold region is carried out which requires low power comparatively. Initially, the design of conventional Op-amp is designed using CADENCE Virtuoso tool GPDK 180nm with a supply voltage of 1.8V and the corresponding gain, phase margin, power of the conventional Op-amp is observed and then, Op-amp with transistors operating in sub threshold region is designed using CADENCE Virtuoso tool GPDK 180nm with a supply voltage of 1.8V and the corresponding gain, phase margin, power is observed. The comparison between these two observations are made and presented. These low power high gain devices are used in various applications like ADC/DAC devices and many medical applications.

Keywords

Op-amp, Phase Margin, Gain, Sub-Threshold Region.

Full Text

   

Adhithan Pon ¹, R. Parameshwaran ¹

Affiliations
1 School of Computing, SASTRA University, Thanjavur - 613401, Tamil Nadu, IN

Abstract

In this paper, we present a new type of odd integer divider topology which consume low power and it uses Mod-N counter, DFF and OR gate. In existing methodology divide by 2 topologies involves only D Flip-Flops (DFF), which realized mostly Common Mode Logic DFF (CML) or True Single Phase Clock (TSPC) based DFF. These were high-speed dividers but no flexibility in this topology i.e. it divides the only power of N. So the proposed divider gives more flexibility to the topology like divided by any real odd integer. While designing a new topology the limitations are operating frequency range, a number of transistor and power consumption. Based on this consideration the 3T NAND and TSPC based Flip-Flop are investigated. The maximum operating frequency of the TSPC divide by 2 is reaches at 2.4 GHz with 1.1931 mw power consumption and is 50% low power consumption compared to the NAND_DFF based frequency divider. Similarly, divide by 3, divide by 5 and divide by 7 also consume low power with less number of transistor compare to the NAND_DFF based frequency divider. So the results show the TSPC is DFF’s more preferable for PLL application and RFIC. The TSPC_DFF based frequency divider designed using 0.18 um CMOS process technology.

Keywords

Frequency Divider, Low Power, Mod-N Counter, PLL, TSCP DFF, 3T NAND Gate.

Full Text

   

A. Naveena Venancias ¹, K. Hariharan ¹, R. Parameshwaran ¹

Affiliations
1 School of Computing, SASTRA University, Thanjavur - 613401, Tamil Nadu, IN

Abstract

Sigma delta ADC is mainly used in resolution based application. But the gain of the sigma delta modulator is low. The main objective of the paper is to design the comparator with high gain. Comparator with low gain cannot drive the load effectively through the entire circuit. This paper was designed and simulated using 180 nm process technology (GPDK 180 nm library) in CADENCE Virtuoso Analog Design Environment. In sigma delta ADC, each block should drive the load effectively to the entire circuit. So that the output will come accurately and delay will be less. Based on that concept, need to design the comparator that can be used in sigma delta ADC. In this point of view, some comparators are analysed. In this paper, analyse the performance of regenerative comparators and op-amp based comparators. And find which will efficient comparator for using at sigma delta modulator. Dynamic comparator, double tail comparator, modified double tail comparator are analysed. The gain of these operational amplifiers are low. So high gain based operational amplifier should be designed. For that, first one op-amp was designed which has 84 dB gain. Using this opamp, one comparator was designed. This comparator has high gain. So it can be used for sigma delta ADC for drive the load. And also it meets certain other constraints like speed and moderate power.

Keywords

CMOS, Opamp Based Comparator, Regenerative Comparators, Sigma Delta ADC, UDSM CMOS Technology.

Full Text