Shibin K. Hassan ¹, P. Reena Monica ²

Affiliations
1 School of Electronics Engineering, VIT University, Chennai Campus, Chennai - 600127, IN
2 School of Electrical Engineering, VIT University, Chennai Campus, Chennai - 600127, IN

Abstract

Objectives: Designing a highly accurate high speed low area Special Function Unit (SFU) is the objective of this work. 32 bit IEEE-754 floating point data format is supported in this system. Methods: The SFU implements elementary functions like inverse, exponential, inverse square ischolar_main, square ischolar_main and logarithm accurately. The unit can be utilized in programmable graphics processors where high performance and high accuracy evaluation is needed. The coefficients of the elementary functions are optimized by Genetic algorithm. The simulations were carried out in Xilinx EDA tool and MATLAB. Synthesis reports were taken from Cadence RTL compiler. Findings: Coefficient optimization and extraction is done using genetic algorithm by doing curve fitting with a second degree polynomial. There is a significant reduction around 40% in the area when constraint piecewise quadratic genetic approximation scheme is used. The number of iterations performed in optimization algorithm is 104. The percentage of error is 0.2578 %. The circuits operated at a frequency of 228MHz and the power dissipation was found to be 3.94 mW. This results in a highly accurate SFU. Conclusion: A significant advantage in area when compared to other previous techniques is obtained. The SFU can be utilized in programmable graphics engine.

Keywords

Elementary Functions, Graphics Processor, Special Function Unit (SFU), Single Precision Computation

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Kodakandla Abhilash ¹, P. Reena Monica ¹

Affiliations
1 School of Electronics Engineering, VIT University, Chennai - 600048,Tamil Nadu, IN

Abstract

Objectives: The objective of this work is to design efficient FFT architectures for real valued signals. For higher value of N, the design of FFT architecture has many butterflies in the same column. A considerable amount of power is needed for such architecture. The hardware complexity also increases. Methods: The throughput depends on the number of input data paths available, which also increases hardware complexity for higher values of N. This work aims at overcoming these shortcomings by employing one of the effective techniques such as parallel pipelined architectures. One butterfly structure is introduced in one column. For handling the complex data paths, different butterfly structures have been introduced using parallel processing and Folding methodology. The design is simulated in Xilinxs14.3, and synthesized in Cadence RTL compiler. Findings: The hardware complexity is reduced by introducing one butterfly structure in one column. Comparison is made between the different radix algorithms and pipelined architectures and Radix-2 multi path delay commutator (R2MDC) in terms of the required number of adders, delay elements, multiplier units, throughput and control complexity. Although the parallel architecture consumes more power, it occupies less area when compared to the R2MDC architecture. Parallel architecture is more area efficient than R2MDC, whereas the radix-2 multi-path delay commutator is simple to implement, since feedback is not needed in the design. Conclusion: This work can be extended to higher order N-values of DIF and DIT-FFT flow graphs.

Keywords

DFT, Fast Fourier Transform (FFT), Folding, Parallel Processing, Pipelining, Radix-2,4,8, Reordering Structures, R2MDC

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Ajintha Elsa Abraham ¹, N. R. Sangeetha ¹, P. Reena Monica ¹

Affiliations
1 SENSE Department, VIT University, Chennai Campus, Chennai - 600127, Tamil Nadu, IN

Abstract

Objective: The objective of this work is to design a Reduced Instruction Set Computing (RISC) processor with Canonic Signed Digit (CSD) recoding. Methods: The incorporation of the CSD recording reduces the number of non-zero bits in the constant word length coefficient. The processor has a dedicated processing unit for the manipulation of floating point numbers. It uses CSD recoded number for the execution of the arithmetic operations such as multiplication. This novel technique reduces the switching activity and in turn resulting in reduction in the power consumed by the processor. Findings: The simulation was carried out using XILINX 14.3 and CADENCE NCLAUNCH. The RISC processor was synthesized with and without the CSD recoding. Although there is a slight increase in the area overhead, the use of ternary number representation in the processor design brought in a power reduction of 56.23%. Conclusions: The CSD recoding was found to be effective in terms of power consumption, making the RISC processor power efficient.

Keywords

CSD Recoding, Floating Point Number, Power Reduction, RISC Processor

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B. V. V. Kiran Kumar ¹, P. Reena Monica ¹

Affiliations
1 School of Electronics Engineering, VIT University, Chennai - 632014, Tamil Nadu, IN

Abstract

Objective: The objective of this work is to efficiently implement a Co-ordinate Rotation Digital Computer (CORDIC) based fast algorithm for power of two length DCT. Methods: The proposed algorithm has some advantages such as regular Cooley-Tukey FFT like data flow, post scaling factor and arithmetic-sequence rotation angles. Using CORDIC algorithm, different types of DCT like four point, eight point and inverse eight point are derived. Usage of trigonometric formula reduces the number of CORDIC. By reusing uniform processing Element cells, architecture for 8-point CORDIC DCT is developed. This is an efficient method for overcoming the problem of lack of synchronization among various rotation angles. Findings: When compared with other known architectures, the proposed 8-point DCT architecture is more efficient in terms of power and area. Power analysis and area estimation are performed for the designed architectures and then further power reduction is carried out using clock gating technique. A power reduction of 4.29% is achieved. The area is also reduced by 0.29%. Conclusion: An efficient VLSI implementation for 8-point DCT by reusing the uniform processing element cells with low hardware complexity is developed.

Keywords

CORDIC, Discrete Cosine Transform (DCT), Processing Element (PE)

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