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Prabhakaran, N.
- GIS Based Microlevel Approach for Hydrogeochemical Studies in Upper Manimuktha Sub Basin, Vellar, South India
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Authors
Affiliations
1 Department of Earth Sciences, Annamalai University, Tamil Nadu, IN
2 Department of Civil Engineering, PSNA College of Engg. & Tech., Tamil Nadu, IN
1 Department of Earth Sciences, Annamalai University, Tamil Nadu, IN
2 Department of Civil Engineering, PSNA College of Engg. & Tech., Tamil Nadu, IN
Source
Indian Journal of Science and Technology, Vol 2, No 11 (2009), Pagination: 5-10Abstract
Groundwater chemical quality studies were carried out in upper Manimuktha sub basin, Vellar, South India. Fifty two groundwater samples were collected from dug and bore well during pre and post monsoon seasons of 2006. The samples were analyzed for various water quality parameters such as pH, Electric Conductivity, Total dissolved solids, Calcium, Magnesium, Sodium, Potassium, Bicarbonate, Carbonate, Sulphate and Chloride. The results were evaluated in detail and compared with WHO water quality standards. An overall assessment of the water samples indicated that the physico and chemical parameters are lies within the permissible limit except in some locations. It is inferred from Piper trilinear diagram that the water is mostly of alkaline earth exceeds alkalies. Gibbs diagram reveals that the overall hydrogeochemical environment of the study area is controlled by the rock water interaction dominance. According to the USSL classification of water quality, it falls under C3 - S1 category. These results were taken in to GIS platform for further processing to understand the spatial variation. Finally, the quality variation is brought out at village level.Keywords
Groundwater, Drinking and Irrigational Quality, GIS, Manimuktha, South IndiaFull Text
References
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- Design and Implementation of Reconfigurable ALU for Signal Processing Applications
Abstract Views :148 |
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Authors
Affiliations
1 Electronics and Communication Engineering, Vel Tech High Tech Dr. Rangarajan Dr. Sakunthala Engineering College, Avadi, Chennai – 600062, Tamil Nadu, IN
2 Electronics and Electrical Engineering, Vel Tech High Tech Dr. Rangarajan Dr. Sakunthala Engineering College, Avadi, Chennai – 600062, Tamil Nadu, IN
1 Electronics and Communication Engineering, Vel Tech High Tech Dr. Rangarajan Dr. Sakunthala Engineering College, Avadi, Chennai – 600062, Tamil Nadu, IN
2 Electronics and Electrical Engineering, Vel Tech High Tech Dr. Rangarajan Dr. Sakunthala Engineering College, Avadi, Chennai – 600062, Tamil Nadu, IN
Source
Indian Journal of Science and Technology, Vol 9, No 2 (2016), Pagination:Abstract
Background/Objectives: The main objective of the paper is to implement a reconfigurable ALU that is a combination of a 32-bit floating point adder/subtractor and integer ALU. The integer ALU performs integer functions and logical operations such as addition, subtraction, shifting and comparison. Methods/Statistical analysis: In this paper, a 32-bit single precision format based on IEEE754 standard for the floating-point unit, with a 23-bit mantissa, 8-bit exponent and 1-bit sign value is considered. Findings: Verilog Hardware Description Language (HDL) is used and simulated by model sim simulator and then synthesized with Spartan3E FPGA. The functional unit uses 25% number of slices, 9% number of slice flip-flops, 18% of 4 input LUTs. From the timing report, the maximum frequency obtained is 81.614MHz. The maximum power obtained by the system is 82.46mW. Applications/Improvements: This can be used for data-parallel and computation intensive applications and in multimedia applications.Keywords
Field Programmable Gate Arrays (FPGA), Hardware Description Language (HDL), Reconfigurable Arithmetic Logic UnitFull Text