Thadigotla Venkata Subbareddy ¹, Chakka Sri Harsha Kaushik ¹, Har Narayan Upadhyay ¹, V. Elamaran ¹

Affiliations
1 Department of ECE, School of EEE, SASTRA University, Thanjavur - 613401, Tamil Nadu, IN

Abstract

Field Programmable Gate Array (FPGA) based designs are the most popular trend towards semiconductor technology evolution. The important subsystem in a configurable logic block is a Look-Up Table (LUT) in the FPGA chip. If the power reduction techniques are implemented in the LUTs, there would be an overall very less power while implementing the design in FPGAs. This study mainly focuses on designing LUTs using Programmable Read Only Memory (PROM) circuits. To implement these LUTs, half adder, full adder, half subtract and full subtractor circuits are chosen with PROM concept. Both the conventional CMOS and pseudo-nMOS style architectures are built for the LUTs. Pseudo-nMOS based LUTs are offering less area and low power compared with conventional CMOS approach. A pseudo-nMOS based full adder LUT design produce 564.5 μm² layout area, which is less compared with 765.5 μm² produced by conventional CMOS full adder LUT. A pseudo-nMOS based full subtractor design produce 1.119 μW dynamic power dissipation, which is less compared with 3.905 μW produced by conventional CMOS full subtractor. Also the design cycle time for FPGAs are much less compared with ASICs. Simulation results are verified using Microwind and Digital Schematic (DSCH) Electronic Computer Aided (CAD) design tools with BSIM4 MOSFET model in 60 nm technology. This study conveys that how the Programmable Read Only Memory (PROM) can act as a Look-Up Table (LUT) within a FPGA architecture. Since engineers are designing the circuits with most care with circuit design, layout design, etc., Application Specific Integrated Circuits (ASIC) are the best at providing low power, high speed and low size at the cost of design cycle time. But with the current semiconductor technology growth, even FPGAs are being manufactured with high speed with more versatile functionalities.

Keywords

CMOS, FPGA, Look-Up Table, Microwind, PROM, Pseudo-nMOS.

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S. Anusha ¹, T. R. Shanmugapriya ¹, S. Venkatalakshmi ¹, Har Narayan Upadhyay ², V. Elamaran ²

Affiliations
1 Department of Electronics and Communication Engineering, School of EEE, SASTRA University, Thanjavur - 613401, Tamil Nadu, IN
2 Department of ECE, School of EEE, SASTRA University, Thanjavur - 613401, Tamil Nadu, IN

Abstract

In the current semiconductor technology evolution, there is a huge demand in designing a low power, high speed adders with less area. As adders are essential components in the data-path of any computer system, adder modules are needed to be enhanced for better performance. One such efficient adder implementation is the Carry Look-Ahead Adder (CLA) which is designed to overcome the latency introduced by rippling effect of carry bits in a conventional Ripple Carry Adder (RCA). Further, the use of this CLA module in the place of Ripple Carry Adder module inside a Carry Select Adder (CSEA) is proposed for increased speed. Also, a novel implementation of adder, making use of the fact that the sum and carry are compliment of one another, except when all the inputs are same is presented. Simulation results show that a 4-bit carry select adder provides a better performance at the cost of power dissipation as 89.211 μW compared with 38.414 μW by a ripple carry adder with 0.12 μm technology processes. In this study, these high speed adders are implemented with the help of the Digital Schematic (DSCH) software tool, Micro wind layout editor tool and Quartus II synthesis software tool. This Quartus II synthesis tool is used for the implementation of adders on Altera EP2C20F484C7 FPGA device. These kinds of adders are further to be extended to build high-speed multipliers which are most important for the applications like digital signal processors, microprocessors, etc.

Keywords

Altera FPGA, Carry Look-Ahead Adders, High Speed Adders, Reduced Full Adder, VLSI.

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R. Pradhisha ¹, N. Iswarya ¹, K. L. V. Gopinath Reddy ¹, Har Narayan Upadhyay ¹, V. Elamaran ¹

Affiliations
1 Department of Electronics and Communication Engineering, School of EEE, SASTRA University, Thanjavur - 613401, Tamil Nadu, IN

Abstract

This study presents self-checking designs for arithmetic and logic circuits using Field Programmable Gate Array (FPGA) design. At present, we are implementing every circuit using VLSI technology because of its excellent features like low power, less area, wide implementation. Since finding error manually is a tedious process, self-checking method would be most wanted. Self-checking circuits are preferable to Automatic Testing Equipment (ATE) because they demand less hardware, low cost and takes very less test application time. The replica construction and pattern recognition are the two methods presented for self-checking logic gates. Self-checking single-bit full adder, 4-bit adder and 2-bit multiplier circuits are implemented and tested on EP2C20F484C7 Altera Cyclone-II FPGA device using Very High-Speed Integrated Circuits Hardware Description Language (VHDL) script. The test data input samples are applied through input switches and the Error/No Error results are obtained on the 7-segment display device. This study discuss in detail about basic self-checking methods with a experimental way. If the complexity of the circuit increases, the components used and the number of connections between the components increases. As a result, the probability of error occurrence increases for complex designs. But this error occurrence can be avoided to the maximum by using self-checking circuits at different build stages in the complex circuit model. The reliability of any system becomes very important especially in the area of applications such space technology, medical image analysis, military communications, etc.

Keywords

Adders, FPGA, Multipliers, Reliability, Self-Checking, Self-Testing.

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